IEICE TRANSACTIONS on Electronics
Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
Summary :
In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E85-C No.2 pp.279-287
- Publication Date
- 2002/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
- Category
- Low-Power Technologies
Authors
Keyword
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Koji INOUE, Vasily G. MOSHNYAGA, Kazuaki MURAKAMI, "Omitting Cache Look-up for High-Performance, Low-Power Microprocessors" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 279-287, February 2002, doi: .
Abstract: In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_279/_p
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@ARTICLE{e85-c_2_279,
author={Koji INOUE, Vasily G. MOSHNYAGA, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Omitting Cache Look-up for High-Performance, Low-Power Microprocessors},
year={2002},
volume={E85-C},
number={2},
pages={279-287},
abstract={In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
T2 - IEICE TRANSACTIONS on Electronics
SP - 279
EP - 287
AU - Koji INOUE
AU - Vasily G. MOSHNYAGA
AU - Kazuaki MURAKAMI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.
ER -
English
