IEICE TRANSACTIONS on Electronics
A W-CDMA Baseband Modem LSI with Multi-Engine Architecture
Summary :
In this paper, a new multi-engine architecture for the baseband modem LSI of W-CDMA systems is proposed. The developed test chip with this architecture is also presented. In the multi-engine architecture, processors and wired logic are combined to obtain both flexibility and low power dissipation. Multiple processors are used in the LSI to lower its operating frequency by distributed processing. A customized processor is used to lower the overhead of multiple processors in terms of LSI scale. The test chip was fabricated with a 0.25-µm process. Its measured power dissipation for simultaneous 384 kbit/s downlink reception and 64 kbit/s uplink transmission was 160 mW.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E85-C No.2 pp.352-358
- Publication Date
- 2002/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
- Category
- Product Designs
Authors
Keyword
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May SUZUKI, Manabu KAWABE, Takashi YANO, Junko KIYOTA, Hirotake ISHII, Tsuyoshi TAMAKI, Nobukazu DOI, "A W-CDMA Baseband Modem LSI with Multi-Engine Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 352-358, February 2002, doi: .
Abstract: In this paper, a new multi-engine architecture for the baseband modem LSI of W-CDMA systems is proposed. The developed test chip with this architecture is also presented. In the multi-engine architecture, processors and wired logic are combined to obtain both flexibility and low power dissipation. Multiple processors are used in the LSI to lower its operating frequency by distributed processing. A customized processor is used to lower the overhead of multiple processors in terms of LSI scale. The test chip was fabricated with a 0.25-µm process. Its measured power dissipation for simultaneous 384 kbit/s downlink reception and 64 kbit/s uplink transmission was 160 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_352/_p
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@ARTICLE{e85-c_2_352,
author={May SUZUKI, Manabu KAWABE, Takashi YANO, Junko KIYOTA, Hirotake ISHII, Tsuyoshi TAMAKI, Nobukazu DOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A W-CDMA Baseband Modem LSI with Multi-Engine Architecture},
year={2002},
volume={E85-C},
number={2},
pages={352-358},
abstract={In this paper, a new multi-engine architecture for the baseband modem LSI of W-CDMA systems is proposed. The developed test chip with this architecture is also presented. In the multi-engine architecture, processors and wired logic are combined to obtain both flexibility and low power dissipation. Multiple processors are used in the LSI to lower its operating frequency by distributed processing. A customized processor is used to lower the overhead of multiple processors in terms of LSI scale. The test chip was fabricated with a 0.25-µm process. Its measured power dissipation for simultaneous 384 kbit/s downlink reception and 64 kbit/s uplink transmission was 160 mW.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A W-CDMA Baseband Modem LSI with Multi-Engine Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 352
EP - 358
AU - May SUZUKI
AU - Manabu KAWABE
AU - Takashi YANO
AU - Junko KIYOTA
AU - Hirotake ISHII
AU - Tsuyoshi TAMAKI
AU - Nobukazu DOI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - In this paper, a new multi-engine architecture for the baseband modem LSI of W-CDMA systems is proposed. The developed test chip with this architecture is also presented. In the multi-engine architecture, processors and wired logic are combined to obtain both flexibility and low power dissipation. Multiple processors are used in the LSI to lower its operating frequency by distributed processing. A customized processor is used to lower the overhead of multiple processors in terms of LSI scale. The test chip was fabricated with a 0.25-µm process. Its measured power dissipation for simultaneous 384 kbit/s downlink reception and 64 kbit/s uplink transmission was 160 mW.
ER -
English
