Characteristics of MOSFET with Non-overlapped Source-Drain to Gate

Hyunjin LEE; Sung-il CHANG; Jongho LEE; Hyungcheol SHIN

Characteristics of MOSFET with Non-overlapped Source-Drain to Gate

Hyunjin LEE, Sung-il CHANG, Jongho LEE, Hyungcheol SHIN

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A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.

Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.5 pp.1079-1085

Publication Date: 2002/05/01

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Type of Manuscript: Special Section PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)

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Hyunjin LEE, Sung-il CHANG, Jongho LEE, Hyungcheol SHIN, "Characteristics of MOSFET with Non-overlapped Source-Drain to Gate" in IEICE TRANSACTIONS on Electronics, vol. E85-C, no. 5, pp. 1079-1085, May 2002, doi: .
Abstract: A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1079/_p

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@ARTICLE{e85-c_5_1079,
author={Hyunjin LEE, Sung-il CHANG, Jongho LEE, Hyungcheol SHIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Characteristics of MOSFET with Non-overlapped Source-Drain to Gate},
year={2002},
volume={E85-C},
number={5},
pages={1079-1085},
abstract={A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - Characteristics of MOSFET with Non-overlapped Source-Drain to Gate
T2 - IEICE TRANSACTIONS on Electronics
SP - 1079
EP - 1085
AU - Hyunjin LEE
AU - Sung-il CHANG
AU - Jongho LEE
AU - Hyungcheol SHIN
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.
ER -