Design of a Conditional Sign Decision Booth Encoder for a High Performance 3232-Bit Digital Multiplier

Minkyu SONG, Kunihiro ASADA

Summary :

In this paper, a high performance 3232-bit multiplier for a DSP core is proposed. The multiplier is composed of a block of Booth Encoder, a block of data compression, and a block of a 64-bit adder. In the block of Booth encoder, a conditional sign decision Booth encoder that reduces the gate delay and power consumption is proposed. In the block of data compression, 4-2 and 9-2 data compressors based on a novel compound logic are used for the efficient compressing of extra sign bit. In the block of 64-bit adder, an adaptive MUX-based conditional select adder with a separated carry generation block is proposed. The proposed 3232-bit multiplier is designed by a full-custom method and there are about 28,000 transistors in an active area of 900 µm 500 µm with 0.25 µm CMOS technology. From the experimental results, the multiplication time of the multiplier is about 3.2 ns at 2.5 V power supply, and it consumes about 50 mW at 100 MHz.

• Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.9 pp.1709-1717
• Publication Date: 2002/09/01
• Type of Manuscript: PAPER
• Category: Electronic Circuits

Authors

Minkyu SONG
Kunihiro ASADA

Keyword

3232-bit multiplier,  conditional sign decision Booth encoder,  compound logic,  9-2 compressor,  64-bit conditional select adder