IEICE TRANSACTIONS on Electronics
A 2 V 2.4 GHz Fully Integrated CMOS LNA with Q-Enhancement Circuit for SOC Design
Summary :
A fully integrated 2 V 2.4 GHz CMOS low-noise amplifier (LNA) is presented in this paper. A negative resistance circuit is used to reduce the parasitic resistors of the on-chip spiral inductor and increase the quality factor (Q). An inductor is added to the common-source and common-gate transistors of the cascode circuit to improve matching and increase power gain. The LNA is designed according to the tsmc 1P4M 0.35 µm process. The parasitic effect of the on-chip spiral inductor was considered. With a 2 V supply, the power gain of the LNA is 19.5 dB, the noise figure is 2.7 dB, and the power dissipation is 15.2 mW. The input third-order intercept point (IIP3) is 0 dBm. The input -1 dB compression point (P-1dB) is -13.9 dBm. The reverse isolation S12 is -44.1 dB.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.6 pp.1050-1055
- Publication Date
- 2003/06/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Chih-Lung HSIAO, Ro-Min WENG, Kun-Yi LIN, "A 2 V 2.4 GHz Fully Integrated CMOS LNA with Q-Enhancement Circuit for SOC Design" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 6, pp. 1050-1055, June 2003, doi: .
Abstract: A fully integrated 2 V 2.4 GHz CMOS low-noise amplifier (LNA) is presented in this paper. A negative resistance circuit is used to reduce the parasitic resistors of the on-chip spiral inductor and increase the quality factor (Q). An inductor is added to the common-source and common-gate transistors of the cascode circuit to improve matching and increase power gain. The LNA is designed according to the tsmc 1P4M 0.35 µm process. The parasitic effect of the on-chip spiral inductor was considered. With a 2 V supply, the power gain of the LNA is 19.5 dB, the noise figure is 2.7 dB, and the power dissipation is 15.2 mW. The input third-order intercept point (IIP3) is 0 dBm. The input -1 dB compression point (P-1dB) is -13.9 dBm. The reverse isolation S12 is -44.1 dB.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_6_1050/_p
Copy
@ARTICLE{e86-c_6_1050,
author={Chih-Lung HSIAO, Ro-Min WENG, Kun-Yi LIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 2 V 2.4 GHz Fully Integrated CMOS LNA with Q-Enhancement Circuit for SOC Design},
year={2003},
volume={E86-C},
number={6},
pages={1050-1055},
abstract={A fully integrated 2 V 2.4 GHz CMOS low-noise amplifier (LNA) is presented in this paper. A negative resistance circuit is used to reduce the parasitic resistors of the on-chip spiral inductor and increase the quality factor (Q). An inductor is added to the common-source and common-gate transistors of the cascode circuit to improve matching and increase power gain. The LNA is designed according to the tsmc 1P4M 0.35 µm process. The parasitic effect of the on-chip spiral inductor was considered. With a 2 V supply, the power gain of the LNA is 19.5 dB, the noise figure is 2.7 dB, and the power dissipation is 15.2 mW. The input third-order intercept point (IIP3) is 0 dBm. The input -1 dB compression point (P-1dB) is -13.9 dBm. The reverse isolation S12 is -44.1 dB.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - A 2 V 2.4 GHz Fully Integrated CMOS LNA with Q-Enhancement Circuit for SOC Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 1050
EP - 1055
AU - Chih-Lung HSIAO
AU - Ro-Min WENG
AU - Kun-Yi LIN
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2003
AB - A fully integrated 2 V 2.4 GHz CMOS low-noise amplifier (LNA) is presented in this paper. A negative resistance circuit is used to reduce the parasitic resistors of the on-chip spiral inductor and increase the quality factor (Q). An inductor is added to the common-source and common-gate transistors of the cascode circuit to improve matching and increase power gain. The LNA is designed according to the tsmc 1P4M 0.35 µm process. The parasitic effect of the on-chip spiral inductor was considered. With a 2 V supply, the power gain of the LNA is 19.5 dB, the noise figure is 2.7 dB, and the power dissipation is 15.2 mW. The input third-order intercept point (IIP3) is 0 dBm. The input -1 dB compression point (P-1dB) is -13.9 dBm. The reverse isolation S12 is -44.1 dB.
ER -
English
