A Rewritable CMOS-FUSE for System-on-Chip with a Differential Cell Architecture in a 0.13 µm CMOS Logic Process

Hiroyuki YAMAUCHI; Yasuhiro AGATA; Masanori SHIRAHAMA; Toshiaki KAWASAKI; Ryuji NISHIHARA; Kazunari TAKAHASHI; Hirohito KIKUKAWA

A Rewritable CMOS-FUSE for System-on-Chip with a Differential Cell Architecture in a 0.13 µm CMOS Logic Process

Hiroyuki YAMAUCHI, Yasuhiro AGATA, Masanori SHIRAHAMA, Toshiaki KAWASAKI, Ryuji NISHIHARA, Kazunari TAKAHASHI, Hirohito KIKUKAWA

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This paper describes a 0.13 µm CMOS Logic process compatible single poly gate type non-volatile (NV) memory with a differential cell architecture, which is tailored for a rewritable FUSE (CMOS-FUSE) for System-on-a Chip (SoC). This paper features the following points; 1) firstly quantified how much important is avoiding any additional process cost and area penalty rather than reducing the area of memory cell itself from the chip cost point of view for the new SoC applications. CMOS FUSE can provide cost-competitive than the high-density NV memories (50-fold higher density with 20% additional cost relative to CMOS FUSE) in the capacity range of 200 kbit for the SoC occupied the logic area of 40 mm². 2) firstly discussed in detail how much the differential cell architecture can change a data retention characteristics including an activation energy (Ea), failure-rate, and tail-bits issues relative to the conventional one based on the measured data of 0.13 µm devices. Based on the measured data retention characteristics at 300, 250, and 200, it is found that the proposed differential approach makes it possible to increase Ea by 1.5 times (from 1.52 eV to 2.23 eV), which means it can be expected to realize a 20000-fold longer data retention characteristics at 105. Even if considering the tail-bit issues for mass-production, an over 700-fold longer data retention characteristics at 105 can be expected while keeping the same failure rate (0.01 ppm) relative to the conventional OR-logical architecture. No significant V_t shifts ( 140 mV and 200 mV) were observed even after applying surge stress of +2200 V from I/O pad and 1000-times cycling of write and erase operations, respectively. In addition, 1024-bit CMOS-FUSE module has been embedded in the SoC without any additional area penalty by being laid out just beneath the power ring for SRAM macro and the stable memory read operation was verified at VDD=1.0 V under a severe I/O switching noise and an unstable VDD/GND condition in the power up sequence.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.10 pp.1664-1672

Publication Date: 2004/10/01

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Type of Manuscript: Special Section PAPER (Special Section on New Era of Nonvolatile Memories)

Category: CMOS Fuse

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Hiroyuki YAMAUCHI, Yasuhiro AGATA, Masanori SHIRAHAMA, Toshiaki KAWASAKI, Ryuji NISHIHARA, Kazunari TAKAHASHI, Hirohito KIKUKAWA, "A Rewritable CMOS-FUSE for System-on-Chip with a Differential Cell Architecture in a 0.13 µm CMOS Logic Process" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 10, pp. 1664-1672, October 2004, doi: .
Abstract: This paper describes a 0.13 µm CMOS Logic process compatible single poly gate type non-volatile (NV) memory with a differential cell architecture, which is tailored for a rewritable FUSE (CMOS-FUSE) for System-on-a Chip (SoC). This paper features the following points; 1) firstly quantified how much important is avoiding any additional process cost and area penalty rather than reducing the area of memory cell itself from the chip cost point of view for the new SoC applications. CMOS FUSE can provide cost-competitive than the high-density NV memories (50-fold higher density with 20% additional cost relative to CMOS FUSE) in the capacity range of 200 kbit for the SoC occupied the logic area of 40 mm². 2) firstly discussed in detail how much the differential cell architecture can change a data retention characteristics including an activation energy (Ea), failure-rate, and tail-bits issues relative to the conventional one based on the measured data of 0.13 µm devices. Based on the measured data retention characteristics at 300, 250, and 200, it is found that the proposed differential approach makes it possible to increase Ea by 1.5 times (from 1.52 eV to 2.23 eV), which means it can be expected to realize a 20000-fold longer data retention characteristics at 105. Even if considering the tail-bit issues for mass-production, an over 700-fold longer data retention characteristics at 105 can be expected while keeping the same failure rate (0.01 ppm) relative to the conventional OR-logical architecture. No significant V_t shifts ( 140 mV and 200 mV) were observed even after applying surge stress of +2200 V from I/O pad and 1000-times cycling of write and erase operations, respectively. In addition, 1024-bit CMOS-FUSE module has been embedded in the SoC without any additional area penalty by being laid out just beneath the power ring for SRAM macro and the stable memory read operation was verified at VDD=1.0 V under a severe I/O switching noise and an unstable VDD/GND condition in the power up sequence.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_10_1664/_p

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@ARTICLE{e87-c_10_1664,
author={Hiroyuki YAMAUCHI, Yasuhiro AGATA, Masanori SHIRAHAMA, Toshiaki KAWASAKI, Ryuji NISHIHARA, Kazunari TAKAHASHI, Hirohito KIKUKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Rewritable CMOS-FUSE for System-on-Chip with a Differential Cell Architecture in a 0.13 µm CMOS Logic Process},
year={2004},
volume={E87-C},
number={10},
pages={1664-1672},
abstract={This paper describes a 0.13 µm CMOS Logic process compatible single poly gate type non-volatile (NV) memory with a differential cell architecture, which is tailored for a rewritable FUSE (CMOS-FUSE) for System-on-a Chip (SoC). This paper features the following points; 1) firstly quantified how much important is avoiding any additional process cost and area penalty rather than reducing the area of memory cell itself from the chip cost point of view for the new SoC applications. CMOS FUSE can provide cost-competitive than the high-density NV memories (50-fold higher density with 20% additional cost relative to CMOS FUSE) in the capacity range of 200 kbit for the SoC occupied the logic area of 40 mm². 2) firstly discussed in detail how much the differential cell architecture can change a data retention characteristics including an activation energy (Ea), failure-rate, and tail-bits issues relative to the conventional one based on the measured data of 0.13 µm devices. Based on the measured data retention characteristics at 300, 250, and 200, it is found that the proposed differential approach makes it possible to increase Ea by 1.5 times (from 1.52 eV to 2.23 eV), which means it can be expected to realize a 20000-fold longer data retention characteristics at 105. Even if considering the tail-bit issues for mass-production, an over 700-fold longer data retention characteristics at 105 can be expected while keeping the same failure rate (0.01 ppm) relative to the conventional OR-logical architecture. No significant V_t shifts ( 140 mV and 200 mV) were observed even after applying surge stress of +2200 V from I/O pad and 1000-times cycling of write and erase operations, respectively. In addition, 1024-bit CMOS-FUSE module has been embedded in the SoC without any additional area penalty by being laid out just beneath the power ring for SRAM macro and the stable memory read operation was verified at VDD=1.0 V under a severe I/O switching noise and an unstable VDD/GND condition in the power up sequence.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - A Rewritable CMOS-FUSE for System-on-Chip with a Differential Cell Architecture in a 0.13 µm CMOS Logic Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 1664
EP - 1672
AU - Hiroyuki YAMAUCHI
AU - Yasuhiro AGATA
AU - Masanori SHIRAHAMA
AU - Toshiaki KAWASAKI
AU - Ryuji NISHIHARA
AU - Kazunari TAKAHASHI
AU - Hirohito KIKUKAWA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2004
AB - This paper describes a 0.13 µm CMOS Logic process compatible single poly gate type non-volatile (NV) memory with a differential cell architecture, which is tailored for a rewritable FUSE (CMOS-FUSE) for System-on-a Chip (SoC). This paper features the following points; 1) firstly quantified how much important is avoiding any additional process cost and area penalty rather than reducing the area of memory cell itself from the chip cost point of view for the new SoC applications. CMOS FUSE can provide cost-competitive than the high-density NV memories (50-fold higher density with 20% additional cost relative to CMOS FUSE) in the capacity range of 200 kbit for the SoC occupied the logic area of 40 mm². 2) firstly discussed in detail how much the differential cell architecture can change a data retention characteristics including an activation energy (Ea), failure-rate, and tail-bits issues relative to the conventional one based on the measured data of 0.13 µm devices. Based on the measured data retention characteristics at 300, 250, and 200, it is found that the proposed differential approach makes it possible to increase Ea by 1.5 times (from 1.52 eV to 2.23 eV), which means it can be expected to realize a 20000-fold longer data retention characteristics at 105. Even if considering the tail-bit issues for mass-production, an over 700-fold longer data retention characteristics at 105 can be expected while keeping the same failure rate (0.01 ppm) relative to the conventional OR-logical architecture. No significant V_t shifts ( 140 mV and 200 mV) were observed even after applying surge stress of +2200 V from I/O pad and 1000-times cycling of write and erase operations, respectively. In addition, 1024-bit CMOS-FUSE module has been embedded in the SoC without any additional area penalty by being laid out just beneath the power ring for SRAM macro and the stable memory read operation was verified at VDD=1.0 V under a severe I/O switching noise and an unstable VDD/GND condition in the power up sequence.
ER -