Graph dissimilarities provide a powerful and ubiquitous approach for applying machine learning algorithms to edge-attributed graphs. However, conventional optimal transport-based dissimilarities cannot handle edge-attributes. In this paper, we propose an optimal transport-based dissimilarity between graphs with edge-attributes. The proposed method, multi-dimensional fused Gromov-Wasserstein discrepancy (MFGW), naturally incorporates the mismatch of edge-attributes into the optimal transport theory. Unlike conventional optimal transport-based dissimilarities, MFGW can directly handle edge-attributes in addition to structural information of graphs. Furthermore, we propose an iterative algorithm, which can be computed on GPUs, to solve non-convex quadratic programming problems involved in MFGW.  Experimentally, we demonstrate that MFGW outperforms the conventional optimal transport-based dissimilarity in several machine learning applications including supervised classification, subgraph matching, and graph barycenter calculation.

A Mach-Zehnder optical modulator with the tunable multimode interference coupler was fabricated using Ti-diffused LiNbO3. The modulation extinction ratio could be voltage controlled to maximize up to 50 dB by tuning the coupler. Optical single-sideband modulation was also achieved with a sideband suppression ratio of more than 30 dB.

This paper proposes a transparent glass quartz antenna for 5G-millimeter-wave-connected vehicles and clarifies the characteristics of signal reception when the glass antennas are placed on the windows of a vehicle traveling in an urban environment. Synthetic fused quartz is a material particularly suited for millimeter-wave devices owing to its excellent low transmission loss. Realizing synthetic fused quartz devices requires accurate micromachining technology specialized for the material coupled with the material technology. This paper presents a transparent antenna comprising a thin mesh pattern on a quartz substrate for installation on a vehicle window. A comparison of distributed transparent antennas and an omnidirectional antenna shows that the relative received power of the distributed antenna system is higher than that of the omnidirectional antenna. In addition, results show that the power received is similar when using vertically and horizontally polarized antennas. The design is verified in a field test using transparent antennas on the windows of a real vehicle.

In this letter, we present a novel single-precision floating-point multiply-accumulator (FNA-MAC) to achieve lower hardware resource, reduced computing latency and improved computing accuracy for continuous dot product operations. By further fusing the normalization and alignment in the traditional FMA algorithm, the proposed architecture eliminates the first N-1 normalization and rounding operations for an N-point dot product, and preserves the precision of interim results in a significant bit size that is twice of that in the traditional methods. The normalization and rounding of the final result is processed at the cost of consuming an additional multiply-add operation. The simulation results show that the improvement in computational accuracy is significant. Meanwhile, when comparing to a recently published FMA design, the proposed FNA-MAC can reduce the slice look-up table/flip-flop resource and computing latency by a fact of 18%, 33.3%, respectively.

This paper derives highly accurate and effective closed-form formulas for the average upper bound on the pairwise error probability (PEP) of the multi-carrier index keying orthogonal frequency division multiplexing (MCIK-OFDM) system with low-complexity detection (i.e., greedy detection) in two-wave with diffuse power (TWDP) fading channels. To be specific, we utilize an exact moment generating function (MGF) of the signal-to-noise ratio (SNR) under TWDP fading to guarantee highly precise investigations of error probability performance; existing formulas for average PEP employ the approximate probability density function (PDF) of the SNR for TWDP fading, thereby inducing inherent approximation error. Moreover, some special cases of TWDP fading are also considered. To quantitatively reveal the achievable modulation gain and diversity order, we further derive asymptotic formulas for the upper bound on the average PEP. The obtained asymptotic expressions can be used to rapidly estimate the achievable error performance of MCIK-OFDM with the greedy detection over TWDP fading in high SNR regimes.

In this letter, we present a new expression of ergodic capacity for two-wave with diffuse power (TWDP) fading channels. The derived formula is relatively concise and consists of well-known functions even in infinite series form. Especially, the truncated approximate expression and asymptotic formula are also presented, which enable us to obtain useful and physical insights on the effect of TWDP fading on the ergodic capacity for various fading conditions.

In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

To effectively analyze the influence of two-wave with diffuse power (TWDP) fading on the achievable error rate performance of binary phase-shift keying (BPSK) signaling, we derive two novel concise asymptotic closed-form bit error rate (BER) formulas. We perform asymptotic analysese based on existing exact and approximate BER formulas, which are obtained from the exact probability density function (PDF) or moment generating function (MGF), and the approximate PDF of TWDP fading. The derived asymptotic closed-form expressions yield explicit insights into the achievable error rate performance in TWDP fading environments. Furthermore, the absolute relative error (ARE) between the exact and approximate coding gains is investigated, from which we also propose a criterion for the order of an approximate PDF, which is more robust than the conventional criterion. Numerical results clearly demonstrate the accuracy of the derived asymptotic formulas, and also support our proposed criterion.

Improving robustness in electrostatic discharge (ESD) protection by inserting drain-side isolated silicon-controlled rectifiers (SCRs) in a high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device was investigated in this paper. Additionally, the effects of anti-ESD reliability in the HV pLDMOS transistors provided by this technique were evaluated. From the experimental data, it was determined that the holding voltage (Vh) values of the pLDMOS with an embedded npn-arranged SCR and discrete thin-oxide (OD) layout on the cathode side increased as the parasitic SCR OD row number decreased. Moreover, the trigger voltage (Vt1) and the Vh values of the pLDMOS with a parasitic pnp-arranged SCR and discrete OD layout on the drain side fluctuated slightly as the SCR OD-row number decreased. Furthermore, the secondary breakdown current (It2) values (i.e., the equivalent ESD-reliability robustness) of all pLDMOS-SCR npn-arranged types increased (>408.4%) to a higher degree than those of the pure pLDMOS, except for npn-DIS_3 and npn-DIS_2, which had low areas of SCRs. All pLDMOS-SCR pnp-arranged types exhibited an increase of up to 2.2A-2.4A, except for the pnp_DIS_3 and pnp_DIS_2 samples; the pnp_DIS_91 increased by approximately 2000.9% (249.1%), exhibiting a higher increase than that of the reference pLDMOS (i.e., the corresponding pnp-stripe type). The ESD robustness of the pLDMOS-SCR pnp-arranged type and npn-arranged type with a discrete OD layout on the SCR cathode side was greater than that of the corresponding pLDMOS-SCR stripe type and a pure pLDMOS, particularly in the pLDMOS-SCR pnp-arranged type.

We estimated the dependence of the perceived depth on luminance ratio by increasing the distance between the front and rear planes of a depth-fused 3-D (DFD) display. When the distance is great, the perceived depth has the tendency of nonlinear dependence on luminance ratio, which is very different from the almost linear dependence in a short-distance conventional DFD display. In a long-distance DFD display, the perceived depth is split to near the front plane at 0-40% of the rear luminance, near the rear plane at 70-100%, and the midpoint of the front and rear planes at 40-60%. Thus, the luminance-ratio dependence of perceived depth changes widely with the distance.

Computer-aided diagnosis (CAD) systems on diffuse lung diseases (DLD) were required to facilitate radiologists to read high-resolution computed tomography (HRCT) scans. An important task on developing such CAD systems was to make computers automatically recognize typical pulmonary textures of DLD on HRCT. In this work, we proposed a bag-of-features based method for the classification of six kinds of DLD patterns which were consolidation (CON), ground-glass opacity (GGO), honeycombing (HCM), emphysema (EMP), nodular (NOD) and normal tissue (NOR). In order to successfully apply the bag-of-features based method on this task, we focused to design suitable local features and the classifier. Considering that the pulmonary textures were featured by not only CT values but also shapes, we proposed a set of statistical measures based local features calculated from both CT values and eigen-values of Hessian matrices. Additionally, we designed a support vector machine (SVM) classifier by optimizing parameters related to both kernels and the soft-margin penalty constant. We collected 117 HRCT scans from 117 subjects for experiments. Three experienced radiologists were asked to review the data and their agreed-regions where typical textures existed were used to generate 3009 3D volume-of-interest (VOIs) with the size of 323232. These VOIs were separated into two sets. One set was used for training and tuning parameters, and the other set was used for evaluation. The overall recognition accuracy for the proposed method was 93.18%. The precisions/sensitivities for each texture were 96.67%/95.08% (CON), 92.55%/94.02% (GGO), 97.67%/99.21% (HCM), 94.74%/93.99% (EMP), 81.48%/86.03%(NOD) and 94.33%/90.74% (NOR). Additionally, experimental results showed that the proposed method performed better than four kinds of baseline methods, including two state-of-the-art methods on classification of DLD textures.

Fused Blocked Pattern Matching is a kind of approximate matching based on Blocked Pattern Matching, and can be used in identification of fused peptides in tumor genomes. In this paper, we propose a new algorithm for fused blocked pattern matching. We give a comparison between Julio's solution and ours, which shows our algorithm is more efficient.

Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.

We investigate in detail the scattering properties and heating characteristics in various commercially available optical fibers and fiber cables when a bubble train forms in the middle of the fiber as a result of the fiber fuse phenomenon that occurs when a high power signal is launched into the fiber. We found theoretically and experimentally that almost all the optical light is scattered at the top of the bubble train. The scattered light heats UV coated fiber, nylon jacketed silica fiber, fire-retardant jacketed fiber (PVC or FRPE jacketed fiber) and fire-retardant fiber cable (PVC or FRPE fiber cable), to around 100, over 200 and over 600, respectively, and finally the fiber burns and is destroyed at a launched optical power of 3 W. Furthermore, it is confirmed that the combustion does not spread when we use fire retardant jacketed fibers.

A reliable antifuse scheme has been very hard to build, which has precluded its implementation in DRAM products. We devised a very reliable multi-cell structure to cope with the large process variation in the DRAM-cell-capacitor type antifuse system. The programming current did not rise above 564 µA even in the nine-cell case. The cumulative distribution of the successful rupture in the multi-cell structure could be curtailed dramatically to less than 15% of the single-cell's case and the recovery problem of programmed cells after the thermal stress (300) had disappeared. In addition, we also presented a Post-Package Repair (PPR) scheme that could be directly coupled to the external high-voltage power rail via an additional pin with small protection circuits, saving the chip area otherwise consumed by the internal pump circuitry. A 1 Gbit DDR SDRAM was fabricated using Samsung's advanced 50 nm DRAM technology, successfully proving the feasibility of the proposed antifuse system implemented in it.

We examined the characteristics of fiber fuse propagation in hole-assisted fibers (HAF). The fiber fuse propagated in the same way as in conventional single-mode fiber (SMF) when the diameter of an inscribed circle linking the air holes (c) was much larger than the diameter of the melted area (Dmelted). The melted area is caused by fiber fuse propagation and Dmelted is assumed to be almost the same size as the plasma. However, when c was much smaller than Dmelted, the fiber fuse did not propagate in HAF with input powers above 15 W at 1480 and 1550 nm. This result indicates that the threshold power of fiber fuse propagation in HAF can be at least 10 times larger than that in conventional SMF in the optical communication band. We also observed the dynamics of fiber fuse termination at a splice point between HAF and a conventional fiber by using a high-speed camera, when c was much smaller than Dmelted. We consider that the reduction in gas density caused by the air holes results in fiber fuse termination. When c was almost the same as Dmelted, we observed a new propagation mode and its dynamics for a fiber fuse with a damage track whose period was approximately 30 times longer than that in conventional SMF. We also made the first observation of a new threshold power (upper threshold) for a fiber fuse.

This letter presents results showing improved field uniformity in a reverberation chamber using quadratic residue diffusers. The optimal occupying ratio of the diffusers on one side wall of the chamber is presented. A reverberation chamber is an alternative to the semi-anechoic chamber, which is widely used for the analysis and measurement of electromagnetic interference and immunity. To analyze the field characteristics, quadratic residue diffusers were designed for the 1-3 GHz frequency band, and the FDTD method was used. At 1-3 GHz, the standard deviation of the test volume in the reverberation chamber was investigated. The reverberation chamber had good field uniformity when quadratic residue diffusers occupy 37.5-50% of one side wall of the reverberation chamber; the field uniformity saturated at the diffuser occupancy rate of 75%.

We propose a low-power eFuse one-time programmable (OTP) memory IP based on a bipolar CMOS DMOS (BCD) process. It is an eFuse OTP memory cell which uses separate transistors that are optimized in program and in read mode. The eFuse cell also uses poly-silicon gates having co-silicide. An asynchronous interface and a separate I/O method are used for the low-power and small-area eFuse OTP memory IP. Additionally, we propose a new circuit protecting a short-circuit current in the VDD-to-VIO voltage level translator circuit while the VDD voltage is being generated by the voltage regulator at power-up. A digital sensing circuit using clocked inverters is used to sense a bit-line (BL) datum. Furthermore, the poly-silicon of the IP is split into n+ poly-silicon and p+ poly-silicon to optimize the eFuse link. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18 µm BCD process is 283.565524.180 µm2. It is measured by manufactured test IPs with Dongbu HiTek's 0.18 µm BCD process that the programming voltage of the n+ gate poly-silicon is about 0.1 V less than that of the p+ gate poly-silicon.

We propose a new speech enhancement method suitable for mobile devices used in the presence of various types of noise. In order to achieve high-performance speech recognition and auditory perception in mobile devices, various types of noise have to be removed under the constraints of a space-saving microphone arrangement and few computational resources. The proposed method can reduce both the directional noise and the diffuse noise under the abovementioned constraints for mobile devices by employing a square microphone array and conducting low-computational-cost processing that consists of multiple null beamforming, minimum power channel selection, and Wiener filtering. The effectiveness of the proposed method is experimentally verified in terms of speech recognition accuracy and speech quality when both the directional noise and the diffuse noise are observed simultaneously; this method reduces the number of word errors and improves the log-spectral distances as compared to conventional methods.

We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52495.78 µm2.