Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
Summary :
Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.1 pp.108-114
- Publication Date
- 2013/01/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.108
- Type of Manuscript
- PAPER
- Category
- Semiconductor Materials and Devices
Authors
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Chizu MATSUMOTO, Yuichi HAMAMURA, Michinobu NAKAO, Kaname YAMASAKI, Yoshikazu SAITO, Shun'ichi KANEKO, "Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 1, pp. 108-114, January 2013, doi: 10.1587/transele.E96.C.108.
Abstract: Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.108/_p
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@ARTICLE{e96-c_1_108,
author={Chizu MATSUMOTO, Yuichi HAMAMURA, Michinobu NAKAO, Kaname YAMASAKI, Yoshikazu SAITO, Shun'ichi KANEKO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs},
year={2013},
volume={E96-C},
number={1},
pages={108-114},
abstract={Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.},
keywords={},
doi={10.1587/transele.E96.C.108},
ISSN={1745-1353},
month={January},}
Copy
TY - JOUR
TI - Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
T2 - IEICE TRANSACTIONS on Electronics
SP - 108
EP - 114
AU - Chizu MATSUMOTO
AU - Yuichi HAMAMURA
AU - Michinobu NAKAO
AU - Kaname YAMASAKI
AU - Yoshikazu SAITO
AU - Shun'ichi KANEKO
PY - 2013
DO - 10.1587/transele.E96.C.108
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2013
AB - Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.
ER -
English
