Ni nanodots (NDs) used as nano-scale top electrodes were formed on a 10-nm-thick Si-rich oxide (SiO$_{mathrm{x}}$)/Ni bottom electrode by exposing a 2-nm-thick Ni layer to remote H$_{2}$-plasma (H$_{2}$-RP) without external heating, and the resistance-switching behaviors of SiO$_{mathrm{x}}$ were investigated from current-voltage ( extit{I--V}) curves. Atomic force microscope (AFM) analyses confirmed the formation of electrically isolated Ni NDs as a result of surface migration and agglomeration of Ni atoms promoted by the surface recombination of H radicals. From local extit{I--V} measurements performed by contacting a single Ni ND as a top electrode with a Rh coated Si cantilever, a distinct uni-polar type resistance switching behavior was observed repeatedly despite an average contact area between the Ni ND and the SiO$_{mathrm{x}}$ as small as $sim$ 1.9 $ imes$ 10$^{-12}$cm$^{2}$. This local extit{I--V} measurement technique is quite a simple method to evaluate the size scalability of switching properties.

In order to analyze an impact of threshold voltage (Vth) fluctuation induced by random telegraph noise (RTN) on LSI circuit design, we measured a 40-nm 6-Tr-SRAM TEG which enables to evaluate individual bit-line current. RTN phenomenon was successfully measured and we also identified that the transfer MOSFET in an SRAM bit-cell was the most sensitive MOSFET. The proposed word line boosting technique, which applies slightly extra stress to the transfer MOSFET, improves about 30% of detecting probability of fail-bit cells caused by RTN.

We have investigated the impact of O2 annealing after SiOx deposition on the switching behavior to gain a better understanding of the resistance switching mechanism, especially the role of oxygen deficiency in the SiOx network. Although resistive random access memories (ReRAMs) with SiOx after 300 annealing sandwiched with Pt electrodes showed uni-polar type resistance switching characteristics, the switching behaviors were barely detectable for the samples after annealing at temperatures over 500. Taking into account of the average oxygen content in the SiOx films evaluated by XPS measurements, oxygen vacancies in SiOx play an important role in resistance switching. Also, the results of conductive AFM measurements suggest that the formation and disruption of a conducting filament path are mainly responsible for the resistance switching behavior of SiOx.

We have fabricated Pt/Si-rich oxide (SiOx)/TiN stacked MIM diodes and studied an impact of the structural asymmetry on their resistive switching characteristics. XPS analyses show that a TiON interfacial layer was formed during the SiOx deposition on TiN by RF-sputtering in an Ar + O2 gas mixture. After the fabrication of Pt top electrodes on the SiOx layer, and followed by an electro-forming process, distinct bi-polar type resistive switching was confirmed. For the resistive switching from high to low resistance states so called SET process, there is no need to set the current compliance. Considering higher dielectric constant of TiON than SiOx, the interfacial TiON layer can contribute to regulate the current flow through the diode. The clockwise resistive switching, in which the reduction and oxidation (Red-Ox) reactions can occur near the TiN bottom electrode, shows lower RESET voltages and better switching endurance than the counter-clockwise switching where the Red-Ox reaction can take place near the top Pt electrode. The result implies a good repeatable nature of Red-Ox reactions at the interface between SiOx and TiON/TiN in consideration of relatively high diffusibility of oxygen atoms through Pt.

Repairing embedded memories (e-memories) on an advanced system-on-chip (SoC) product is a key technique used to improve product yield. However, increasing the die area of SoC products equipped with various types of e-memories on the die is an issue. A fuse scheme can be used to resolve this issue. However, several fuse schemes that have been proposed to decrease the die area result in an increased repair time. Therefore, in this paper, we propose a novel fuse scheme that decreases both die area and repair time. Moreover, our approach is applied to a 65 nm SoC product. The results indicate that the proposed fuse scheme effectively decreases the die area and repair time of advanced SoC products.

A new information detection method has been proposed for a very fast and efficient search engine. This method is implemented on hardware system using FPGA. We take advantages of Content Addressable Memory (CAM) which has an ability of matching mode for designing the system. The CAM blocks have been designed using available memory blocks of the FPGA device to save access times of the whole system. The entire memory can return multi-match results concurrently. The system operates based on the CAMs for pattern matching, in a parallel manner, to output multiple addresses of multi-match results. Based on the parallel multi-match operations, the system can be applied for pattern matching with various required constraint conditions without using any search principles. The very fast multi-match results are achieved at 60 ns with the operation frequency 50 MHz. This increases the search performance of the information detection system which uses this method as the core system.

We have studied resistance-switching properties of RF sputtered Si-rich oxides sandwiching with Pt electrodes. By sweeping bias to the top Pt electrode, non-polar type resistance switching was observed after a forming process. In comparison to RF sputtered TiOx case, significant small current levels were obtained in both the high resistance state (HRS) and the low resistance state (LRS). And, even with decreasing SiOx thickness down to 8 nm from 40 nm, the ON/OFF ratio in resistance-switching between HRS and LRS as large as 103 was maintained. From the analysis of current-voltage characteristics for Pt/SiOx on p-type Si(100) and n-type Si(100), it is suggested that the red-ox (REDction and OXidation) reaction induced by electron fluence near the Pt/SiOx interface is of importance for obtaining the resistance-switching behavior.

In this paper, it is shown that our fabricated MTJ of 60180 nm2, which is connected to the MOSFET in series by 3 levels via and 3 levels metal line, can dynamically operate with the programming current driven by 0.14 µm CMOSFET. In our measurement of transient characteristic of fabricated MTJ, the pulse current, which is generated by the MOSFET with an applied pulse voltage of 1.5 V to its gate, injected to the fabricated MTJ connected to the MOSFET in series. By using the current measurement technique flowing in MTJ with sampling period of 10 nsec, for the first time, we succeeded in monitor that the transition speed of the resistance change of 60180 nm2 MTJ is less than 30 ns with its programming current of 500 µA and the resistance change of 1.2 kΩ.

A radio frequency identification tag LSI operating with the carrier frequency of 13.56 MHz as well as storing nonvolatile information in embedded ferroelectric random access memory (FeRAM) has been developed. A full wave rectifier composed of PMOS transistor diodes and NMOS transistor switches achieves RF-to-DC power conversion efficiency over 54%. The entire 16 kbits write and read transaction time can be reduced to 2.1 sec by the use of FeRAM, which corresponds to 2.2 times speed enhancement over conventional EEPROM based tag LSIs. The communication range of the FeRAM based tag LSI can be effectively improved by storing antitheft information in a ferroelectric nonvolatile flip-flop, which can reduce the power consumption of FeRAM from 27 µW to 5 µW. The communication range for the antitheft gate system becomes 70 cm.