IEICE TRANSACTIONS on Fundamentals
An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory
Summary :
A new information detection method has been proposed for a very fast and efficient search engine. This method is implemented on hardware system using FPGA. We take advantages of Content Addressable Memory (CAM) which has an ability of matching mode for designing the system. The CAM blocks have been designed using available memory blocks of the FPGA device to save access times of the whole system. The entire memory can return multi-match results concurrently. The system operates based on the CAMs for pattern matching, in a parallel manner, to output multiple addresses of multi-match results. Based on the parallel multi-match operations, the system can be applied for pattern matching with various required constraint conditions without using any search principles. The very fast multi-match results are achieved at 60 ns with the operation frequency 50 MHz. This increases the search performance of the information detection system which uses this method as the core system.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.10 pp.1708-1717
- Publication Date
- 2012/10/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.1708
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Duc-Hung LE, Katsumi INOUE, Masahiro SOWA, Cong-Kha PHAM, "An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 10, pp. 1708-1717, October 2012, doi: 10.1587/transfun.E95.A.1708.
Abstract: A new information detection method has been proposed for a very fast and efficient search engine. This method is implemented on hardware system using FPGA. We take advantages of Content Addressable Memory (CAM) which has an ability of matching mode for designing the system. The CAM blocks have been designed using available memory blocks of the FPGA device to save access times of the whole system. The entire memory can return multi-match results concurrently. The system operates based on the CAMs for pattern matching, in a parallel manner, to output multiple addresses of multi-match results. Based on the parallel multi-match operations, the system can be applied for pattern matching with various required constraint conditions without using any search principles. The very fast multi-match results are achieved at 60 ns with the operation frequency 50 MHz. This increases the search performance of the information detection system which uses this method as the core system.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.1708/_p
Copy
@ARTICLE{e95-a_10_1708,
author={Duc-Hung LE, Katsumi INOUE, Masahiro SOWA, Cong-Kha PHAM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory},
year={2012},
volume={E95-A},
number={10},
pages={1708-1717},
abstract={A new information detection method has been proposed for a very fast and efficient search engine. This method is implemented on hardware system using FPGA. We take advantages of Content Addressable Memory (CAM) which has an ability of matching mode for designing the system. The CAM blocks have been designed using available memory blocks of the FPGA device to save access times of the whole system. The entire memory can return multi-match results concurrently. The system operates based on the CAMs for pattern matching, in a parallel manner, to output multiple addresses of multi-match results. Based on the parallel multi-match operations, the system can be applied for pattern matching with various required constraint conditions without using any search principles. The very fast multi-match results are achieved at 60 ns with the operation frequency 50 MHz. This increases the search performance of the information detection system which uses this method as the core system.},
keywords={},
doi={10.1587/transfun.E95.A.1708},
ISSN={1745-1337},
month={October},}
Copy
TY - JOUR
TI - An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1708
EP - 1717
AU - Duc-Hung LE
AU - Katsumi INOUE
AU - Masahiro SOWA
AU - Cong-Kha PHAM
PY - 2012
DO - 10.1587/transfun.E95.A.1708
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2012
AB - A new information detection method has been proposed for a very fast and efficient search engine. This method is implemented on hardware system using FPGA. We take advantages of Content Addressable Memory (CAM) which has an ability of matching mode for designing the system. The CAM blocks have been designed using available memory blocks of the FPGA device to save access times of the whole system. The entire memory can return multi-match results concurrently. The system operates based on the CAMs for pattern matching, in a parallel manner, to output multiple addresses of multi-match results. Based on the parallel multi-match operations, the system can be applied for pattern matching with various required constraint conditions without using any search principles. The very fast multi-match results are achieved at 60 ns with the operation frequency 50 MHz. This increases the search performance of the information detection system which uses this method as the core system.
ER -
English
