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[Keyword] multi-match(5hit)

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  • A CAM-Based Information Detection Hardware System for Fast Image Matching on FPGA

    Duc-Hung LE  Tran-Bao-Thuong CAO  Katsumi INOUE  Cong-Kha PHAM  

     
    PAPER-Electronic Circuits

      Vol:
    E97-C No:1
      Page(s):
    65-76

    In this paper, the authors present a CAM-based Information Detection Hardware System for fast, exact and approximate image matching on 2-D data, using FPGA. The proposed system can be potentially applied to fast image matching with various required search patterns, without using search principles. In designing the system, we take advantage of Content Addressable Memory (CAM) which has parallel multi-match mode capability and has been designed, using dual-port RAM blocks. The system has a simple structure, and does not employ any Central Processor Unit (CPU) or complicated computations.

  • Design a Fast CAM-Based Exact Pattern Matching System on FPGA and 0.18µm CMOS Process

    Duc-Hung LE  Katsumi INOUE  Cong-Kha PHAM  

     
    LETTER-VLSI Design Technology and CAD

      Vol:
    E96-A No:9
      Page(s):
    1883-1888

    A CAM-based matching system for fast exact pattern matching is implemented on a hardware system with FPGA and ASIC. The system has a simple structure, and does not employ any Central Processor Unit (CPU) as well as complicated computations. We take advantage of Content Addressable Memory (CAM) which has an ability of parallel multi-match mode for designing the system. The system is applied to fast pattern matching with various required search patterns without using search principles. In this paper, the authors present a CAM-based system for fast exact pattern matching on 2-D data.

  • An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory

    Duc-Hung LE  Katsumi INOUE  Masahiro SOWA  Cong-Kha PHAM  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E95-A No:10
      Page(s):
    1708-1717

    A new information detection method has been proposed for a very fast and efficient search engine. This method is implemented on hardware system using FPGA. We take advantages of Content Addressable Memory (CAM) which has an ability of matching mode for designing the system. The CAM blocks have been designed using available memory blocks of the FPGA device to save access times of the whole system. The entire memory can return multi-match results concurrently. The system operates based on the CAMs for pattern matching, in a parallel manner, to output multiple addresses of multi-match results. Based on the parallel multi-match operations, the system can be applied for pattern matching with various required constraint conditions without using any search principles. The very fast multi-match results are achieved at 60 ns with the operation frequency 50 MHz. This increases the search performance of the information detection system which uses this method as the core system.

  • Threshold Equalization for On-Line Signature Verification

    Isao NAKANISHI  Hiroyuki SAKAMOTO  Yoshio ITOH  Yutaka FUKUI  

     
    LETTER-Cryptography and Information Security

      Vol:
    E91-A No:8
      Page(s):
    2244-2247

    In on-line signature verification, complexity of signature shape can influence the value of the optimal threshold for individual signatures. Writer-dependent threshold selection has been proposed but it requires forgery data. It is not easy to collect such forgery data in practical applications. Therefore, some threshold equalization method using only genuine data is needed. In this letter, we propose three different threshold equalization methods based on the complexity of signature. Their effectiveness is confirmed in experiments using a multi-matcher DWT on-line signature verification system.

  • Multi-Matcher On-Line Signature Verification System in DWT Domain

    Isao NAKANISHI  Hiroyuki SAKAMOTO  Naoto NISHIGUCHI  Yoshio ITOH  Yutaka FUKUI  

     
    PAPER-Information Hiding

      Vol:
    E89-A No:1
      Page(s):
    178-185

    This paper presents a multi-matcher on-line signature verification system which fuses the verification scores in pen-position parameter and pen-movement angle one at total decision. Features of pen-position and pen-movement angle are extracted by the sub-band decomposition using the Discrete Wavelet Transform (DWT). In the pen-position, high frequency sub-band signals are considered as individual features to enhance the difference between a genuine signature and its forgery. On the other hand, low frequency sub-band signals are utilized as features for suppressing the intra-class variation in the pen-movement angle. Verification is achieved by the adaptive signal processing using the extracted features. Verification scores in the pen-position and the pen-movement angle are integrated by using a weighted sum rule to make total decision. Experimental results show that the fusion of pen-position and pen-movement angle can improve verification performance.