In this paper, it is shown that our fabricated MTJ of 60180 nm2, which is connected to the MOSFET in series by 3 levels via and 3 levels metal line, can dynamically operate with the programming current driven by 0.14 µm CMOSFET. In our measurement of transient characteristic of fabricated MTJ, the pulse current, which is generated by the MOSFET with an applied pulse voltage of 1.5 V to its gate, injected to the fabricated MTJ connected to the MOSFET in series. By using the current measurement technique flowing in MTJ with sampling period of 10 nsec, for the first time, we succeeded in monitor that the transition speed of the resistance change of 60180 nm2 MTJ is less than 30 ns with its programming current of 500 µA and the resistance change of 1.2 kΩ.

In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/ 1-poly Gate 0.14 µm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60180 nm2 achieves a large change in resistance of 3.52 kΩ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320 µA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.

In order to realize Integrated Circuits (IC) with operation over the 10 GHz range, conventional CMOS logic faces critical issues, such as increasing power consumption, and difficulty to aggressively scale the device size and so on. To overcome this issue, we have proposed Current Controlled-MOS Current Mode Logic (CC-MCML) to realize the reduction of power consumption and the enhancement of the operation speed in logic circuits without scaling the gate length of the MOSFET, and confirmed the performance of these circuits both theoretically and experimentally. In the CC-MCML it is extremely important to control the input voltage of the MOSFET used as the constant current source in order to make the base voltage of the input signal and the output signal equivalent. In this paper, we propose CC-MCML/MTJ (Magnetic Tunnel Junction) circuit, which is one type of nonvolatile memory hybrid circuit technology. A more stable and precise operation is realized by cutting the range of the input voltage of the constant current source, and it is shown that the operation of CC-MCML/MTJ Hybrid Circuit enables us to suppress the base voltage difference due to the Vth fluctuation in comparison with the conventional CC-MCML. These results imply the high potential of Si-CMOS/Spintronics Hybrid technologies for future IC.

We have succeeded in fabricating 180 nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180 nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔVB. The ΔVB, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53 V to 0.69 V, and threshold voltage of PMOS fluctuates in the range of -0.47 V to -0.67 V, the CC-MCML technique is able to suppress ΔVB within only 30 mV, where as the conventional MCML technique caused maximum ΔVB of 1.0 V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.

In this paper, we propose the novel Dynamic Feedback (DF-) MCML technique for high-speed and high-gain MCML type latch. The concept of the proposed DF-MCML technique is as follows; the output node signal is feedbacked to the input node in Sampling-Mode, and the output node is opened from the input node in Holding-Mode. It is shown by analytic theory that by this dynamic feedback sequence, both stability and sensibility of latch in Sampling-Mode is exponentially improved, and the gain of latch in Holding-Mode is drastically increased. Finally, we have numerically investigated the circuit performance of the novel DF-MCML type latch in comparison with the conventional MCML type latch by using P-Spice simulator. The maximum operation frequency of 180 nm DF-MCML type latch reaches over 20 GHz that is 2 times than the conventional MCML type latch. It is made clear that the proposed novel Dynamic Feedback MCML technique is suitable for over 10 GHz high-speed and high-gain Si ULSIs.