IEICE TRANSACTIONS on Electronics
Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation
Summary :
We have succeeded in fabricating 180 nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180 nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔVB. The ΔVB, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53 V to 0.69 V, and threshold voltage of PMOS fluctuates in the range of -0.47 V to -0.67 V, the CC-MCML technique is able to suppress ΔVB within only 30 mV, where as the conventional MCML technique caused maximum ΔVB of 1.0 V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.5 pp.760-766
- Publication Date
- 2011/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.760
- Type of Manuscript
- Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
- Category
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Masashi KAMIYANAGI, Takuya IMAMOTO, Takeshi SASAKI, Hyoungjun NA, Tetsuo ENDOH, "Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 5, pp. 760-766, May 2011, doi: 10.1587/transele.E94.C.760.
Abstract: We have succeeded in fabricating 180 nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180 nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔVB. The ΔVB, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53 V to 0.69 V, and threshold voltage of PMOS fluctuates in the range of -0.47 V to -0.67 V, the CC-MCML technique is able to suppress ΔVB within only 30 mV, where as the conventional MCML technique caused maximum ΔVB of 1.0 V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.760/_p
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@ARTICLE{e94-c_5_760,
author={Masashi KAMIYANAGI, Takuya IMAMOTO, Takeshi SASAKI, Hyoungjun NA, Tetsuo ENDOH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation},
year={2011},
volume={E94-C},
number={5},
pages={760-766},
abstract={We have succeeded in fabricating 180 nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180 nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔVB. The ΔVB, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53 V to 0.69 V, and threshold voltage of PMOS fluctuates in the range of -0.47 V to -0.67 V, the CC-MCML technique is able to suppress ΔVB within only 30 mV, where as the conventional MCML technique caused maximum ΔVB of 1.0 V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.},
keywords={},
doi={10.1587/transele.E94.C.760},
ISSN={1745-1353},
month={May},}
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TY - JOUR
TI - Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation
T2 - IEICE TRANSACTIONS on Electronics
SP - 760
EP - 766
AU - Masashi KAMIYANAGI
AU - Takuya IMAMOTO
AU - Takeshi SASAKI
AU - Hyoungjun NA
AU - Tetsuo ENDOH
PY - 2011
DO - 10.1587/transele.E94.C.760
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2011
AB - We have succeeded in fabricating 180 nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180 nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔVB. The ΔVB, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53 V to 0.69 V, and threshold voltage of PMOS fluctuates in the range of -0.47 V to -0.67 V, the CC-MCML technique is able to suppress ΔVB within only 30 mV, where as the conventional MCML technique caused maximum ΔVB of 1.0 V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.
ER -
English
