A High-Speed and Multi-Chip WTA/MAX Circuit Design Based on Averaged-Value Comparison Approach
Summary :
This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E87-C No.10 pp.1724-1729
- Publication Date
- 2004/10/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
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Kuo-Huang LIN, Chi-Sheng LIN, Bin-Da LIU, "A High-Speed and Multi-Chip WTA/MAX Circuit Design Based on Averaged-Value Comparison Approach" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 10, pp. 1724-1729, October 2004, doi: .
Abstract: This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_10_1724/_p
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@ARTICLE{e87-c_10_1724,
author={Kuo-Huang LIN, Chi-Sheng LIN, Bin-Da LIU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Speed and Multi-Chip WTA/MAX Circuit Design Based on Averaged-Value Comparison Approach},
year={2004},
volume={E87-C},
number={10},
pages={1724-1729},
abstract={This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - A High-Speed and Multi-Chip WTA/MAX Circuit Design Based on Averaged-Value Comparison Approach
T2 - IEICE TRANSACTIONS on Electronics
SP - 1724
EP - 1729
AU - Kuo-Huang LIN
AU - Chi-Sheng LIN
AU - Bin-Da LIU
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2004
AB - This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.
ER -
English
