This paper proposes an efficient reference image sharing method for the image-division parallel video encoding architecture. This method efficiently reduces the amount of data transfer by using pre-transfer with area prediction and on-demand transfer with a transfer management table. Experimental results show that the data transfer can be reduced to 19.8-35.3% of the conventional method on average without major degradation of coding performance. This makes it possible to reduce the required bandwidth of the inter-chip transfer interface by saving the amount of data transfer.

A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40 GHz, and the demonstration of a 47-Gbps SFQ 22 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4 K with a two-stage 1-W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (~10 Gbps/ch) and SFQ circuits (>40 GHz). An SFQ 22 switch chip, in which the MUX/DEMUX and an SFQ 22 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10 kA/cm2. An SFQ 22 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with φ 50-µm InSn solder bumps. An SFQ 22 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47 Gbps for the first time.

Advances in smart card technology encourages smart card use in more sensitive applications, such as storing important information and securing application. Smart cards are however vulnerable to side channel attacks. Power consumption and electromagnetic radiation of the smart card can leak information about the secret data protected by the smart card. Our paper describes two possible hardware countermeasures that protect against side channel information leakage. We show that power analysis can be prevented by adopting photo-coupling techniques. This method involves the use of LED with photovoltaic cells and photo-couplers on the power, reset, I/O and clock lines of the smart card. This method reduces the risk of internal data bus leakage on the external data lines. Moreover, we also discuss the effectiveness of reducing electromagnetic radiation by using embedded metal plates.

In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.

This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.

An experimental 640-Gbit/s ATM switching system is described. The switching system is scalable and quasi-non-blocking and uses hardware self-rearrangement in a three-stage network. Hardware implementation results for the switching system are presented. The switching system is fabricated using advanced 0.25-µm CMOS devices, high-density multi-chip-module (MCM) technology, and optical wavelength-division-multiplexing (WDM) interconnection technology. A scalable 80-Gbit/s switching module is fabricated in combination with a developed scalable-distributed-arbitration technique, and a WDM interconnection system that connects multiple 80-Gbit/s switching modules is developed. Using these components, an experimental 640-Gbit/s switching system is partially constructed. The 640-Gbit/s switching system will be applied to future broadband ATM networks.