IEICE TRANSACTIONS on Electronics
Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories
Summary :
In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.
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- IEICE TRANSACTIONS on Electronics Vol.E87-C No.11 pp.1847-1855
- Publication Date
- 2004/11/01
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- Type of Manuscript
- Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
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Yusuke OIKE, Makoto IKEDA, Kunihiro ASADA, "Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 11, pp. 1847-1855, November 2004, doi: .
Abstract: In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_11_1847/_p
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@ARTICLE{e87-c_11_1847,
author={Yusuke OIKE, Makoto IKEDA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories},
year={2004},
volume={E87-C},
number={11},
pages={1847-1855},
abstract={In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 1847
EP - 1855
AU - Yusuke OIKE
AU - Makoto IKEDA
AU - Kunihiro ASADA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2004
AB - In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.
ER -
English
