A reaction-diffusion computer is a large-scale array of elementary processors, micro-volumes of chemical medium, which act, change their states determined by chemical reactions, concurrently and interact locally, via local diffusion of chemical species; it transforms data to results, both represented by concentration profiles of chemical species, by traveling and colliding waves in spatially extended chemical media. We show that reaction-diffusion processors, simulated or experimental, can solve a variety of tasks, including computational geometry, robot navigation, logics and arithmetics.

A new approach for ultra-low-power LSIs based on quantum devices is presented and its present status and critical issues are discussed with a brief background review on the semiconductor nanotechnology. It is a hexagonal binary decision diagram (BDD) quantum logic circuit approach suitable for realization of ultra-low-power logic/memory circuits to be used in new applications such as intelligent quantum (IQ) chips embedded in the ubiquitous network environment. The basic concept of the approach, circuit examples showing its feasibility, growth of high density nanostructure networks by molecular beam epitaxy (MBE) for future LSI implementation, and the key processing issues including the device isolation issue are addressed.

Circuit techniques to realize stable recall operation and virtually unlimited read/program cycle operations in ferroelectric memory based nonvolatile (NV) SRAM composed of six-transistor and four-ferroelectric capacitor cells have been developed. Unlimited program cycle operation independent of ferroelectric material characteristics is realized by proper control of plate lines. Reliability evaluation results show that the developed memory cell has sufficient operation margin after stresses of temperature, fatigue, DC bias. Application of NV-SRAM to programmable logic devices has been discussed with a prototype of dynamically programmable gate arrays.

In this paper, a new computing paradigm suitable for analog circuit systems is described in comparison to the digital circuit systems. The analog circuit systems have some disadvantages especially in terms of accuracy and stability, but there are some applications that don't require accuracy or stability in circuit component. The new computing concept for such applications, 'inaccurate' information processing, or 'rough' information processing, is proposed and described as well as some examples of such applications.

A very long instruction word (VLIW) digital signal processor (DSP), called ODiN, which could execute six instructions in a single cycle simultaneously, is designed and fabricated using 0.25 µm 1-ploy 5-metal standard cell static CMOS process. The ODiN core delivers maximum 600 MIPS with 100 MHz system clock. In order to achieve high performance operation, the designed core includes compact register files, orthogonal instruction set, single cycle operations for most instructions, and parallel processing based on software scheduling. In addition, a Viterbi decoder processor and a FFT processor that are embedded make it possible to implement software defined radio (SDR) applications efficiently.

This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.

The carbon nanotube field-effect transistors show the hysteresis characteristic in their electrical characteristics owing to the amorphous carbon around the carbon nanotube. It is shown here the reduction of the hysteresis characteristic by the refining process applied repeatedly to the carbon nanotube. Moreover, after the refining processes, the transconductance of carbon nanotube field-effect transistor becomes 2.0 µS the ten times larger than before the refining process. Almost all carbon nanotubes without the refining processes, grown by thermal chemical vapor deposition, show the p type semiconductor characteristics. After the refining processes on the other hand, almost all carbon nanotube show the ambipolar type semiconductor characteristics.

Quantum dots are one of the possible building blocks for the quantum computing device. We discuss on use of carbon nanotubes for fabrication of the quantum dot, in terms of their unique physical properties and energy scales which might be advantageous for functionalities of the quantum computing device. Simple schemes of a charge qubit and a spin qubit are described, followed by the current status of the fabrication and transport measurements of the nanotube quantum dot. Based on the basic properties and the estimated energy scales of the dot, we discuss advantages and problems of the carbon nanotube for the quantum computing device. The nanotube quantum dot may have a great advantage for the spin qubit.

An experimental model of a redox microarray, which provides a foundation for constructing future massively parallel molecular computers, is proposed. The operation of a redox microarray is confirmed, using an experimental setup based on an array of microelectrodes with analog integrated circuits.

A multifunctional Boolean logic circuit composed of single-electron transistors (SETs) was fabricated and its operation demonstrated. The functions of Boolean logic can be changed by the half-period phase shift of the Coulomb-blockade (CB) oscillation of some SETs in the circuit, and an automatic control based on a feedback process is used to attain an exact shift. The amount of charges in the memory node (MN), which is capacitively coupled to the SET, controls the phase of the CB oscillation, and the output signal of the SET controls the amount of charge in the MN during the feedback process. This feedback process automatically adjusts SET output characteristics in such a way that it is used for the multifunctional Boolean logic. We experimentally demonstrated the automatic phase control and examined the speed of the feedback process by SPICE circuit simulation combined with a compact analytical SET model. The simulation revealed that programming time could be of the order of a few ten nanoseconds, thereby promising high-speed switching of the functions of the multifunctional Boolean logic circuit.

This paper introduces a methodology for simulating single-electron-transistor (SET)-based multiple-valued logics (MVLs). First, a physics-based analytical model for SET is described, and then a procedure for extracting parameters from measured characteristics is explained. After that, simulated and experimental results for basic MVL circuits are compared. As an advanced example of SET-based logics, a latched parallel counter, which is one of the most important components in arithmetic circuits, is newly designed and analyzed by a simulation. It is found that a SET-based 7-3 counter can be constructed with less than 1/10 the number of devices needed for a conventional circuit and can operate at a moderate speed with 1/100 the conventional power consumption.

This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and 1 MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.

In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.

This paper presents circuit techniques using pulse-width and pulse-phase modulation (PWM/PPM) approaches for VLSI implementation of nonlinear dynamical systems. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain, and also approximately implement continuous-time dynamics. Arbitrary nonlinear transformation functions are generated by the process in which a PPM signal samples a voltage or current source whose waveform in the time domain has the same shape as the desired transformation function. Because a shared arbitrary nonlinear voltage or current waveform generator can be constructed by digital circuits and D/A converters, high flexibility and real-time controllability are achieved. By using one of these new techniques, we have designed and fabricated a CMOS chaos circuit with arbitrary 1-D maps using a 0.6 µm CMOS process, and demonstrate from the experimental results that the new chaos circuit successfully generated various chaos with 7.5-7.8 bit precision by using logistic, tent and chaotic-neuron maps.

Ultrahigh-speed compact flash analog-to-digital converters (ADCs) using resonant-tunneling diodes (RTDs) have been designed to demonstrate a high potential of RTD circuits. Novel multi-input subtraction gates are introduced to the encoder to obtain a compact circuit configuration. By assuming 0.1-µm InP-based RTD/HEMT technology, circuit simulations of 4-bit 10-GHz flash ADCs are carried out. It is found that the device counts of the ADC with an 8-input gate are one third that of the ADC with 4-input gates. This leads to a reduction in the power dissipation by 50%. In addition, bandwidths of more than 20 GHz have been obtained for 4-bit and 5-bit ADCs at a sampling frequency of 10 GHz.

A novel Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) architecture using the Multiple-Valued Source-Coupled Logic (MVSCL) is proposed to implement special-purpose processors. An MV-FPVLSI consists of identical cells, which are connected to 8-neighborhood ones. To reduce the complexity of the interconnection block between two cells in an MV-FPVLSI, a bit-serial fine-grain pipeline architecture is introduced which allows single-wire data transmission and as a result, the data-transmission delay becomes very small in comparison with that of a conventional FPGA. To reduce the number of switches in the interconnection block further, a cell, using multiple-valued source-coupled logic circuits, is proposed, where the input currents can be linearly summed just by wiring without using any active devices. Not only the data, but also the control signal can be superposed by linear summation. As a result, no input switch is required which contributes to smaller data transmission delay. Moreover, an arbitrary 2-input logic function can be generated by linear summation of the input currents and threshold operations using these reconfigurable MVSCL circuits. As the MVSCL circuit has high driving capability in comparison with that of an equivalent CMOS circuit, high-speed logic operation is also possible while maintaining low power.

A new circuit technique based on pass-gate logic with dynamic supply-voltage and clock-frequency control is proposed for a low-power motion-vector detection VLSI processor. Since the pass-gate logic style has potential advantages that have small equivalent stray capacitance and small number of short-circuit paths, its circuit implementation makes it possible to reduce the power dissipation with maintaining high-speed switching capability. In case the calculation result is obtained on the way of calculation steps, additional power saving is also achieved by combining the pass-gate logic circuitry with a mechanism that dynamically scales down the supply voltage and the clock frequency while maintaining the calculation throughput. As a typical example, a sum of absolute differences (SAD) unit in a motion-vector detection VLSI processor is implemented and its efficiency in power saving is demonstrated.

Reconfigurable logic circuitry has special importance because the popularity of Field Programmable Gate Arrays (FPGA) based applications. A reconfigurable logic based on FGMOS transistors, where a single stage can perform binary operations as well as state machines, is presented. The use of the proposed logic allows the integration of several stages into a single chip because their small area requirement, low voltage and low power characteristics.

In this paper we present a new type of CMOS Time-of-Flight (TOF) range image sensor based on CMOS Active Pixel Sensor (APS) techniques. The TOF sensor features high-speed and efficient photo-charge transfer that is essential in range imaging. The rapid and efficient charge transfer is made possible by the use of a high-gain inverting amplifier and capacitors connected alternatively to the feedback path. This leads to the cost-effective implementation of the system. The analysis of simulation results suggests that the proposed technique can achieve a sufficient range resolution of millimeters to centimeters depending on the maximum measured range, if the noise is dominated by photon shot noise.

This paper presents a novel architecture to solve two problems of existing FPGAs : the large delay and area due to complex programmable switch blocks, and the large area due to coarse-grain logic blocks that are underutilized to a great degree. A mesh-connected cellular array based on a bit-serial pipeline architecture is introduced to minimize complexity of switch blocks. A fine-grain logic block architecture with a functionality of a bit-serial adder is presented to minimize the number of inputs and outputs of the logic block since increase in the number of inputs and outputs directly increases the complexity of a switch block. For an area-efficient design, the logic block is implemented based on a hybrid of a programmable logic gate and a dedicated carry logic. The hybrid architecture allows us to use a small lookup table to implement the logic gate. Moreover, the carry logic uses a functional pass-gate that merges both logic and storage functions compactly. The performance of the fine-grain field-programmable VLSI (FPVLSI) is evaluated to be more than 2 times higher than that of a coarse-grain FPVLSI.

A finite impulse response (FIR) core based on the cascoded class AB SI technique is presented for low power wireless transceivers. Accomplished through both architectural and circuit developments, the filter's features include high speed, low power consumption, small silicon area and compatibility with standard CMOS process. For feasibility and performance assessments, an 8-tap 16 MS/s SI FIR filter with 5-bit coefficients and a 31-tap 80 MS/s SI matched filter (MF) for despreading task in future WCDMA receivers are demonstrated via simulations.

We propose an ultra low power watch-dog circuit with the use of MOSFETs operation under subthreshold characteristics. The circuit monitors the amount of the product degradation because the subthreshold current of MOSFET emulates the rate of the general chemical reaction. Its operation was verified with both SPICE simulation and the measurement of the prototype chip. The new circuit embedded in a tag attached to any product could dynamically monitor the degradation regardless of storage conditions.

A new common-bus architecture with temporal and spatial parallel access capabilities under wire-resource constraint is proposed to transfer vast quantities of data between modules inside a VLSI chip. Since bus controllers are distributed into modules, the proposed bus architecture can directly transfer data from one module to another without any central bus control unit like a Direct Memory Access (DMA) controller, which enables to reduce communication steps for data transfer between modules. Moreover, when a start address and the number of block data in both source/destination modules are determined at the first step of a data-transfer scheme, no additional address setting for the data transfer is required in the rest of the scheme, which allows us to use all the wire resources as only the "data bus." Therefore, the bus function is dynamically programmed, which results in achieving high throughput of bus communication. For example, in case of a 64-line common bus, it is evaluated that the maximum data throughput in the proposed architecture with dynamic bus-function programming is four times higher than that in the conventional DMA bus architecture with fixed 32-bit-address/32-bit-data buses.

An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290 360 µm² and 240 280 µm², respectively.

This paper presents an asynchronous data transfer scheme using 2-color 2-phase dual-rail encoding based on a differential operation and its circuit realization. The proposed encoding enables seamless asynchronous data transfer without inserting a spacer, because each logic value is represented by two kinds of codewords with dual-rail, called "color" data. Since the difference x-x between components of a codeword (x,x) becomes constant in every valid state, the data-arrival state can be detected by calculating the difference x-x. From the viewpoint of circuit implementation, during the state transition, since the dual-rail x and x are defined so as to transit differentially, the compatibility with a comparator using a differential amplifier becomes high, which results in reduction of the cycle time. It is evaluated using HSPICE simulation with a 0.18 µm CMOS technology that communication speed using the proposed dual-rail encoding becomes 1.4 times faster than that using conventional dual-rail encoding.

We have investigated the pretilt angle of liquid crystal (LC) molecules induced by photo-alignment films of polyimide (Azo-PI) containing azobenzene in the backbone structure. To generate finite pretilt angles, the Azo-PI film with inclined alignment of the backbone structure was prepared by a double light-exposure method. In this method the corresponding polyamic acid (Azo-PAA) film was first exposed to linearly polarized ultraviolet/visible (UV/VIS) light (LP-light) at normal incidence, and then oblique angle irradiation of unpolarized UV/VIS light (UP-light) was performed in the plane of incidence perpendicular to the polarization direction of the LP-light. Repeated photo-isomerization reactions of azobenzene induce the alignment of the Azo-PAA backbone structure. By thermally imidizing the photo-treated film we obtained a thermally and optically stable Azo-PI film. The orientational distribution of the Azo-PI backbone structure was determined by measuring the polarized infrared absorption spectra as a function of the sample rotation angle and the angle of incidence. The pretilt angle of LC molecules was determined by a crystal rotation method. We found that the average inclination angle of the Azo-PI backbone structure increased with the UP-light exposure. The pretilt angle of LC molecules, measured from the surface plane, also increased with the UP-light exposure. We succeeded in generating a pretilt angle of 3. The relation between the LC pretilt angle and the average inclination angle of the Azo-PI backbone structure is discussed.

Location control of grains by µ-Czochralski process with excimer-laser is a powerful tool for realizing high performance single-crystalline Si TFTs (c-Si TFTs). This study reports the behavior of p-channel single-crystalline Si TFTs fabricated inside a location-controlled grain by µ-Czochralski method. Self-aligned p-channel single-crystalline Si TFTs is fabricated with a top gate structure having ECR-PECVD SiO₂ as gate insulator. The field effect hole mobility of 250 cm²/Vs and subthreshold swing of 0.29 V/dec. are obtained successfully. Effects of active Si thickness and boron channel doping on the characteristics of the c-Si TFTs were studied.

We have developed a two-dimensional flat-panel imager (FPI) utilizing conventional amorphous silicon (a-Si) thin film transistor (TFT) technology for AM-LCDs, and we have made a prototype. We can experimentally manufacture the FPI basically by utilizing conventional production lines of AM-LCDs, because the imager is based on the TFT array for AM-LCDs. The TFT performs both switching and photo-detecting functions itself. Using the FPI, we can capture monochrome images in real time, and can also achieve full-color images by introducing time-sequential driving based on a color backlight system with RGB-LEDs. The reliability of the TFT under bias and irradiation stress caused by capturing images is maintained by introducing an original driving method and processing the captured image. By making use of advantages the FPI has over conventional imaging systems, we hope that the FPI will be a useful compact imaging device for documents, pictures, fingerprints, and the like.

A double surface light emission backlight that uses single light-guide plate, has been developed for illumination of two liquid-crystal displays (LCD) on its front and rear, to be used in a cellular phone. The light-guide plate has a trapezoid cross-section with arrays of optical micro deflector and micro prism on the front and the rear surfaces, respectively. Propagated light, forward and backward, inside the light-guide plate are controlled and directed toward LCDs using only two prism sheets with internal reflection characteristic, each for the front and the rear. Only three optical components and four light-emitting diodes (LEDs) are used in the new structure compared with ten components and six LEDs of the current type. Comparing with the current type, the thickness and power consumption of the new backlight are reduced by a factor of 0.59 and 0.67, respectively.

We propose a new cell configuration which newly employs discharge deactivation film (DDF). DDF is formed on MgO surface in stripe figure to cover it around the boundary of neighboring display lines. DDF prevents discharge cross talk between the lines even in case of stripe rib structure by virtue of its low secondary electron emission coefficient (γ_i). DDF also makes better address discharge response because it presumably moves address discharge closer to the surface dischage gap. On behalf of mass productivity for large size PDPs DDF is formed by simple screen-printing and firing method. And it consists of very fine Al₂O₃ grains without any inorganic binder. Such DDF is visually transparent and then helpful for high luminance and luminous efficiency. In addition to it, such DDF is presumably equipped with gas purifying character and then helpful for deep blue color and good white color balance accordingly. Further, DDF combined with sustain electrodes in specific figure which we call "CAPABLE DDF" brings about so high luminous efficiency for stripe rib structure as it may surpass box rib one. This probably means that vertically open discharge space in stripe rib structure is advantageous for high luminous efficiency. In our latest work for 46 inch-high definition PDPs, 2.1 lm/W and 1200 cd/m² were both achieved under practical driving condition. Still it will be as high as 2.4 lm/W if each sustain electrode is shared by neighboring display lines. CAPABLE DDF allows more tolerance in DDF printing process. It also makes optical cross talk negligible even in stripe rib structure. And its durability against long time operation proved to have no specific problem. This presumably means that re-landing of sputtered MgO never reaches DDF surface. We believe this new technology can promise the future of stripe rib.

The driving frequency dependence of EL characteristics were investigated in thick ceramic insulating type thin-film electroluminescent (TFEL) devices with various Mn-activated Y₂O₃-based phosphor thin-film emitting layers driven by a sinusoidal wave voltage. High luminous efficiencies of approximately 10 and 1 lm/W were obtained in the TFEL devices driven at 60 Hz and 1 kHz, respectively. The difference in luminous efficiency was mainly caused by the increase of input power in 1 kHz-driven-devices resulting from a dielectric loss of a thick BaTiO₃ ceramic sheet used as the insulating layer. The correlation between the sound emission from the devices and the effective power consumed in the devices was found with variations in both the applied voltage and the frequency. The higher input power of the 1 kHz-driven-device may be attributable to sound emissions resulting from the piezo-electricity of BaTiO₃ ceramics.

Overall picture quality of a liquid crystal display (LCD) is changed by viewing conditions. An evaluation method of overall picture quality was proposed for LCDs. However, the estimation values calculated by the evaluation method differed from the subjective evaluation values, when viewing angle changed in the vertical direction. In this study, the coefficients of impairment in the evaluation equation were obtained by the multiple regression analysis using subjectively evaluated data. The evaluation method of overall picture quality was improved by weighting factors using these coefficients. As the result, the good estimation accuracy was obtained even if the viewing angle was changed both in the horizontal and vertical directions individually.

Our goal is to realize an extra-large stereoscopic display in the open air for use by the general public. We have developed a stereoscopic large display by use of a full-color LED panel. Although the developed display enables viewers to view the stereoscopic images without any special glasses, it is necessary for the viewers to move to stand within the viewing areas. Movements of the viewers are considered to depend on arrangements of viewing areas. The purpose of this paper is to investigate the movements of viewers who watch different designs of stereoscopic LED displays with a parallax barrier, including conventional designs to provide multiple perspective images and designs to eliminate pseudoscopic viewing areas, and evaluate the performance of different viewing areas based on the obtained paths of the viewers. We have developed a real-time measurement system of a viewer's position by use of a camera on the ceiling. We have recorded the viewing movements caused by the shift of viewing areas. It was found that the viewers moved to stand on orthoscopic viewing positions. The movements of viewers who move to find a viewing area have been recorded with different designs of stereoscopic LED displays that provide different viewing areas. We have calculated the lateral moving time of the viewers'movements. It is shown that the elimination of pseudoscopic viewing areas reduces the lateral moving time. Thus, the real-time measurement system of a viewer's position has been utilized for evaluation of performance of the different designs of stereoscopic LED displays.

This paper presents a new type of optical probe designed to detect magnetic near-fields with high accuracy in the gigahertz range. Its probe head consists of a loop antenna element doubly loaded with LiNbO₃ electro-optic crystals. Through an optical technique, it can work as a conventional double-loaded loop probe without metallic cables or an electrical hybrid junction. We examined probe characteristics for magnetic field detection up to 20 GHz. We confirmed that the probe can measure magnetic fields near a microstrip line in the gigahertz range and can suppress influence of electric fields.

In this paper, the amplitude coefficient in each mode of leakage waves is calculated by using the amplitude level of the electric field about these unwanted waves under Ministry of Economy, Trade and Industry (METI) definition for measuring the leakage waves irradiated from door portion at the time of microwave oven manufacture, and the percentage of each mode included in leakage waves is also calculated by using finite difference time domain (FDTD) method. Furthermore, shielding effectiveness (SE) of choke structure for suppressing the leakage waves is calculated using combined waves composed of higher order modes as each percentages. As a result, the percentage of each mode included in the leakage waves is examined quantitatively. The approximation analysis for the SE of the choke structure can also be carried out. Therefore, efficient method for evaluating the door structure of the oven at the time of manufacture has been established without the use of the memory in the calculation.

This letter presents a novel method to design a power distribution network with highly accurate impedance characteristic. Based on the PBEC (path-based equivalent circuit) model and the network synthesis, the proposed design method exploits simple arithmetic expressions to calculate the electrical parameters of a power distribution network. It directly calculates and determines the size of on-chip decoupling capacitors, the size and location of off-chip decoupling capacitors, and the effective inductances of the package power bus. To evaluate the accuracy of the proposed method, it was applied to a test board with size of 12.5 cm 12.5 cm and with plane-to-plane distance of 200 µm. The proposed method successfully designed a power distribution network keeping its impedance characteristic under 1 Ω with frequency range of 100 kHz-1 GHz. The proposed design method requires negligible computation when compared with conventional PEEC (partial elements equivalent circuit) model-based design approaches, but the simulation results of both methods are almost identical. Consequently, the proposed method enables simple, fast and accurate design of power-distribution networks, which gives economic and practical solutions for commercial tools.

The relation between resonant frequency of micromirror with vertical combdrives and applied voltage between the upper and lower comb teeth was analyzed. Resonant frequency of the micromirror was controlled by stiffness of the torsion hinge. Resonant frequency of the mirror was proportional to the applied voltage between the upper and lower comb teeth at the same tilt angle.

An efficient VLSI architecture for 1-D lifting DWT is proposed in this paper. To achieve higherhardware utilization and higher throughput, the computations of all resolution levels are folded to both the same high-pass and low-pass filters. Besides, the number of registers in the folded architecture is minimized by using the generalized lifetime analysis. Owing to its regular and flexible structure, the design can be extended easily into different resolution levels, and its area is independent of the length of the 1-D input sequence. Compared with other known architectures, our design requires the least computing time for 1-D lifting DWT.