The fabrication process of a novel Si interface control layer (Si ICL)-based oxide-free insulated gate structure for InP metal-insulator-semiconductor field effect transistors (MISFETs) was successfully characterized and optimized using in-situ reflection of high-energy electron diffraction (RHEED), Raman scattering spectroscopy, X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) techniques, and applied for fabrication of MISFETs. RHEED observation indicated that the optimum initial thickness of the Si ICL with single crystal pseudomorphic growth of Si on InP is 10 . Raman scattering spectroscopy showed existence of surface strain on InP covered with the Si ICL without changing LO-phonon peak width, indicating that the Si ICL is grown in a pseudomorphic fashion. A detailed XPS analysis showed that Fermi level pinning was largely reduced by the growth of the Si ICL and its partial electron cyclotron resonance (ECR) plasma nitridation realizing an optimum Si ICL thickness of 5 with a good interface to SiNx. C-V measurement confirmed that the optimum Si ICL-based gate formation process realized a full swing of Fermi level almost over the entire bandgap. The fabricated MISFET using the optimum gate structure exhibited excellent gate controllability and stable operation with a low gate leakage currents.

A novel InGaAs/InAlAs insulated gate (IG) pseudomorphic high electron mobility transistor (PHEMT) having a silicon interface control layer (Si ICL) is successfully fabricated and characterized. Systematic efforts to characterize and optimize the insulated gate structure and the PHEMT fabrication process were made by using in-situ X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) techniques. This led to successful fabrication of a novel IG-PHEMT showing excellent stable DC characteristics with a good pinch off and a high transconductance (177 mS/mm), very small gate leakage currents, very high gate breakdown voltages (about 40 V) and respectable RF characteristics fT = 9 GHz and fmax=38 GHz.

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

We investigate the origin of non-ideal transfer characteristics in graphene-based three-branch nano-junction (TBJ) devices. Fabricated graphene TBJs often show asymmetric nonlinear voltage transfer characteristic, although symmetric one should appear ideally. A simple model considering the contact resistances in two input electrodes is deduced and it suggests that the non-ideal characteristic arises from inequality of the metal-graphene contact resistances in the inputs. We fabricate a graphene TBJ device with electrically equal contacts by optimizing the contact formation process and almost ideal nonlinear characteristic was successfully demonstrated.

With advent of the ubiquitous network era and due to recent progress of III-V nanotechnology, the present III-V heterostructure microelectronics will turn into what one might call III-V heterostructure nanoelectronics, and may open up a new future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V heterostructure nanoelectronics will be formed on nanostructure networks formed by combination of top-down and bottom-up approaches. In addition to communication devices, emerging devices include high speed digital LSIs, various sensors, various smart-chips, quantum LSIs and quantum computation devices covering varieties of application areas. Ultra-low power quantum LSIs may become brains of smart chips and other nano-space systems. Achievements of new functions and higher performances and their on chip integration are key issues. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale.

A new approach for ultra-low-power LSIs based on quantum devices is presented and its present status and critical issues are discussed with a brief background review on the semiconductor nanotechnology. It is a hexagonal binary decision diagram (BDD) quantum logic circuit approach suitable for realization of ultra-low-power logic/memory circuits to be used in new applications such as intelligent quantum (IQ) chips embedded in the ubiquitous network environment. The basic concept of the approach, circuit examples showing its feasibility, growth of high density nanostructure networks by molecular beam epitaxy (MBE) for future LSI implementation, and the key processing issues including the device isolation issue are addressed.