Surface passivation process of GaN utilizing electron-cyclotron-resonance (ECR) excited plasma has been characterized and optimized for realization of stable operation in GaN-based high-power/high-frequancy electronic devices. From XPS analysis, the NH4OH treatment as well as the ECR-N2 and ECR-H2 plasma treatments were found to be effective in removing natural oxide and contaminants from the GaN surface. The SiNx/GaN structure prepared by the ECR excited plasma chemical vapor deposition (ECR-CVD) process showed better C-V behavior compared to the SiO2/GaN structure. Surface treatment process using the ECR plasma improved interface properties and achieved the Dit value of 21011 cm-2 eV-1 or less. An estimate of the valence band offset by XPS showed that the present SiNx/n-GaN structure has a type-I band lineup, suitable for the surface passivation of GaN-based devices. No pronounced stress remained at the SiNx/GaN interface, which was confirmed by Raman spectroscopy.

In order to clarify the mechanism of gate leakage in AlGaN/GaN heterostructure field effect transistors (HFETs), temperature (T)-dependent current-voltage (I-V) characteristics of Ni/n-AlGaN Schottky contact were measured in detail. Large deviations from the thermionic emission transport were observed in I-V-T behavior with anomalously large reverse leakage currents. An analysis based on the thin surface barrier (TSB) model showed that the nitrogen-vacancy-related near-surface donors play a dominant role in the leakage through the AlGaN Schottky interface. As a practical scheme for suppressing the leakage currents, use of an insulated gate (IG) structure was investigated. As the insulator, Al2O3 was selected, and an Al2O3 IG structure was formed on the AlGaN/GaN heterostructure surface after an ECR-N2 plasma treatment. An in-situ XPS analysis exhibited successful formation of an ultrathin stoichiometric Al2O3 layer which has a large conduction band offset of 2.1 eV at the Al2O3/Al0.3Ga0.7N interface. The fabricated Al2O3 IG HFET achieved pronounced reduction of gate leakage, resulting in the good gate control of drain currents up to VGS = +3 V. The maximum drain saturation current and transconductance were 0.8 A/mm and 120 mS/mm, respectively. No current collapse was observed in the Al2O3 IG-HFETs, indicating a remarkable advantage of the present Al2O3-based insulated gate and passivation structure.

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

With advent of the ubiquitous network era and due to recent progress of III-V nanotechnology, the present III-V heterostructure microelectronics will turn into what one might call III-V heterostructure nanoelectronics, and may open up a new future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V heterostructure nanoelectronics will be formed on nanostructure networks formed by combination of top-down and bottom-up approaches. In addition to communication devices, emerging devices include high speed digital LSIs, various sensors, various smart-chips, quantum LSIs and quantum computation devices covering varieties of application areas. Ultra-low power quantum LSIs may become brains of smart chips and other nano-space systems. Achievements of new functions and higher performances and their on chip integration are key issues. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale.