IEICE TRANSACTIONS on Electronics
Fast Learning Algorithms for Self-Organizing Map Employing Rough Comparison WTA and its Digital Hardware Implementation
Summary :
This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E87-C No.11 pp.1787-1794
- Publication Date
- 2004/11/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
- Category
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Hakaru TAMUKOH, Keiichi HORIO, Takeshi YAMAKAWA, "Fast Learning Algorithms for Self-Organizing Map Employing Rough Comparison WTA and its Digital Hardware Implementation" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 11, pp. 1787-1794, November 2004, doi: .
Abstract: This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_11_1787/_p
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@ARTICLE{e87-c_11_1787,
author={Hakaru TAMUKOH, Keiichi HORIO, Takeshi YAMAKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fast Learning Algorithms for Self-Organizing Map Employing Rough Comparison WTA and its Digital Hardware Implementation},
year={2004},
volume={E87-C},
number={11},
pages={1787-1794},
abstract={This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.},
keywords={},
doi={},
ISSN={},
month={November},}
Copy
TY - JOUR
TI - Fast Learning Algorithms for Self-Organizing Map Employing Rough Comparison WTA and its Digital Hardware Implementation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1787
EP - 1794
AU - Hakaru TAMUKOH
AU - Keiichi HORIO
AU - Takeshi YAMAKAWA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2004
AB - This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.
ER -
English
