A direction-oriented spatial interpolation technique for image de-interlacing is presented in this letter. The experimental results demonstrate that our method achieves excellent performance in terms of both objective and subjective image quality. The proposed algorithm also has a very computationally simple structure, and proves to be a good candidate for low-cost hardware interpolator.

In H.264, the context-based adaptive variable length coding (CAVLC) is used for lossless compression. Direct table-lookup implementation requires higher cost because it employs a larger memory to produce the encoded results. In this letter, we present a more efficient technique for CAVLC implementation. Compared with those previous CAVLC chips, our design requires the lowest hardware cost.

An efficient VLSI architecture for 1-D lifting DWT is proposed in this paper. To achieve higherhardware utilization and higher throughput, the computations of all resolution levels are folded to both the same high-pass and low-pass filters. Besides, the number of registers in the folded architecture is minimized by using the generalized lifetime analysis. Owing to its regular and flexible structure, the design can be extended easily into different resolution levels, and its area is independent of the length of the 1-D input sequence. Compared with other known architectures, our design requires the least computing time for 1-D lifting DWT.

Correct and quick generation of a membership function is the key point when we implement a real-time fuzzy logic controller. In this Letter, we presented two efficient VLSI architectures, one to generate triangle-shaped and the other to generate trapezoid-shaped membership functions. Simulation results show that our designs require lower hardware cost but achieve faster working rate.

In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.21.2 mm2. The power dissipation of the chip is about 0.4 W at the clock rate of 80 MHz.

Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.