IEICE TRANSACTIONS on Fundamentals
VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform
Summary :
Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.1 pp.275-279
- Publication Date
- 2004/01/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- VLSI Design Technology and CAD
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Keyword
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Pei-Yin CHEN, "VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 1, pp. 275-279, January 2004, doi: .
Abstract: Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_1_275/_p
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@ARTICLE{e87-a_1_275,
author={Pei-Yin CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform},
year={2004},
volume={E87-A},
number={1},
pages={275-279},
abstract={Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 275
EP - 279
AU - Pei-Yin CHEN
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2004
AB - Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.
ER -
English
