IEICE TRANSACTIONS on Information
VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter
Summary :
In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.2
- Publication
- IEICE TRANSACTIONS on Information Vol.E85-D No.12 pp.1893-1897
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- VLSI Systems
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Pei-Yin CHEN, "VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 12, pp. 1893-1897, December 2002, doi: .
Abstract: In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.2
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_12_1893/_p
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@ARTICLE{e85-d_12_1893,
author={Pei-Yin CHEN, },
journal={IEICE TRANSACTIONS on Information},
title={VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter},
year={2002},
volume={E85-D},
number={12},
pages={1893-1897},
abstract={In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.2
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter
T2 - IEICE TRANSACTIONS on Information
SP - 1893
EP - 1897
AU - Pei-Yin CHEN
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2002
AB - In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.2
ER -
English
