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[Author] Yusuke OIKE(4hit)

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  • A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method

    Yusuke OIKE  Makoto IKEDA  Kunihiro ASADA  

     
    PAPER-Electronic Circuits

      Vol:
    E86-C No:11
      Page(s):
    2320-2328

    A high-speed 3-D camera has a future possibility of wide variety of application fields such as quick inspection of industrial components, observation of motion/destruction of a target object, and fast collision prevention. In this paper, a row-parallel position detector for a high-speed 3-D camera based on a light-section method is presented. In our row-parallel search method, the positions of activated pixels are quickly detected by a row-parallel search circuit in pixel and a row-parallel address acquisition of O(log N) cycles in N-pixel horizontal resolution. The architecture keeps high-speed position detection in high pixel resolution. We have designed and fabricated the prototype position sensor with a 12816 pixel array in 0.35 µm CMOS process. The measurement results show it achieves quick activated-position acquisition of 450 ns for "beyond-real-time" 3-D imaging and visual feedback. The high-speed position detection of the scanning sheet beam is demonstrated.

  • Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition

    Yusuke OIKE  Makoto IKEDA  Kunihiro ASADA  

     
    PAPER-Electronic Circuits

      Vol:
    E87-C No:12
      Page(s):
    2164-2171

    In this paper, we present a pixel-level color image sensor with efficient ambient light suppression using a modulated RGB flashlight to support a recognition system. The image sensor employs bidirectional photocurrent integrators for pixel-level demodulation and ambient light suppression. It demodulates a projected flashlight with suppression of an ambient light at short intervals during an exposure period. In the imaging system using an RGB modulated flashlight, every pixel provides innate color and depth information of a target object for color-based categorization and depth-key object extraction. We have designed and fabricated a prototype chip with 6464 pixels using a 0.35 µm CMOS process. Color image reconstruction and time-of-flight range finding have been performed for the feasibility test.

  • High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit

    Yusuke OIKE  Makoto IKEDA  Kunihiro ASADA  

     
    PAPER-Integrated Electronics

      Vol:
    E85-C No:8
      Page(s):
    1651-1658

    We propose a high-sensitivity and wide-dynamic-range position sensor using logarithmic-response and correlation circuit. The 3-D measurement system using the proposed position sensor has advantages to applications, for example a walking robot and a recognition system on vehicles, which require both of availability in various backgrounds and safe light projection for human eyes. The position sensor with a 64 64 pixel array has been developed and successfully tested. We describe the sensitivity of position detection as SBR (Signal-to-Background Ratio). The minimum SBR of the sensor is -13.9 dB lower than standard sensors. High sensitivity under -10 dB SBR is realized in a dynamic range of 41.7 dB in terms of background illumination. Experimental results of position detection and 3-D measurement in a strong background illumination are also presented.

  • Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories

    Yusuke OIKE  Makoto IKEDA  Kunihiro ASADA  

     
    PAPER

      Vol:
    E87-C No:11
      Page(s):
    1847-1855

    In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.