High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access
Summary :
An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E87-C No.11 pp.1923-1927
- Publication Date
- 2004/11/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
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Shinsaku SHIMIZU, Toshimasa MATSUOKA, Kenji TANIGUCHI, "High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 11, pp. 1923-1927, November 2004, doi: .
Abstract: An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_11_1923/_p
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@ARTICLE{e87-c_11_1923,
author={Shinsaku SHIMIZU, Toshimasa MATSUOKA, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access},
year={2004},
volume={E87-C},
number={11},
pages={1923-1927},
abstract={An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access
T2 - IEICE TRANSACTIONS on Electronics
SP - 1923
EP - 1927
AU - Shinsaku SHIMIZU
AU - Toshimasa MATSUOKA
AU - Kenji TANIGUCHI
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2004
AB - An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290
ER -
English
