A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor

Toshihiro HATTORI; Kenji OGURA

A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor

Toshihiro HATTORI, Kenji OGURA

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In low-power embedded processors design, stand-by power constraint is also important with average power and operation frequency. Multi-threshold-voltage cells are used in the design and the ratio of low-Vth cells should be controlled. On the other hand, physical synthesis flow is indispensable to achieve high performance and short design time. This paper proposes a physical synthesis methodology under the restriction of maximum low-Vth cell ratio. The experimental results show that our method can achieve only 4 MHz slower logic within 5% margin of the target low-Vth ratio. We have applied this design flow in an application processor design and the designed processor demonstrates 360 MIPS at 200 MHz only with 80 mW at 1.0 V, namely 4500 MIPS/W and 4.2 mA leakage current without any power-cut mode.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.520-526

Publication Date: 2004/04/01

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Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)

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Toshihiro HATTORI, Kenji OGURA, "A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 4, pp. 520-526, April 2004, doi: .
Abstract: In low-power embedded processors design, stand-by power constraint is also important with average power and operation frequency. Multi-threshold-voltage cells are used in the design and the ratio of low-Vth cells should be controlled. On the other hand, physical synthesis flow is indispensable to achieve high performance and short design time. This paper proposes a physical synthesis methodology under the restriction of maximum low-Vth cell ratio. The experimental results show that our method can achieve only 4 MHz slower logic within 5% margin of the target low-Vth ratio. We have applied this design flow in an application processor design and the designed processor demonstrates 360 MIPS at 200 MHz only with 80 mW at 1.0 V, namely 4500 MIPS/W and 4.2 mA leakage current without any power-cut mode.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_4_520/_p

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@ARTICLE{e87-c_4_520,
author={Toshihiro HATTORI, Kenji OGURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor},
year={2004},
volume={E87-C},
number={4},
pages={520-526},
abstract={In low-power embedded processors design, stand-by power constraint is also important with average power and operation frequency. Multi-threshold-voltage cells are used in the design and the ratio of low-Vth cells should be controlled. On the other hand, physical synthesis flow is indispensable to achieve high performance and short design time. This paper proposes a physical synthesis methodology under the restriction of maximum low-Vth cell ratio. The experimental results show that our method can achieve only 4 MHz slower logic within 5% margin of the target low-Vth ratio. We have applied this design flow in an application processor design and the designed processor demonstrates 360 MIPS at 200 MHz only with 80 mW at 1.0 V, namely 4500 MIPS/W and 4.2 mA leakage current without any power-cut mode.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 520
EP - 526
AU - Toshihiro HATTORI
AU - Kenji OGURA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2004
AB - In low-power embedded processors design, stand-by power constraint is also important with average power and operation frequency. Multi-threshold-voltage cells are used in the design and the ratio of low-Vth cells should be controlled. On the other hand, physical synthesis flow is indispensable to achieve high performance and short design time. This paper proposes a physical synthesis methodology under the restriction of maximum low-Vth cell ratio. The experimental results show that our method can achieve only 4 MHz slower logic within 5% margin of the target low-Vth ratio. We have applied this design flow in an application processor design and the designed processor demonstrates 360 MIPS at 200 MHz only with 80 mW at 1.0 V, namely 4500 MIPS/W and 4.2 mA leakage current without any power-cut mode.
ER -