IEICE TRANSACTIONS on Electronics
Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm
Summary :
In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E103-C No.11 pp.685-692
- Publication Date
- 2020/11/01
- Publicized
- 2020/05/13
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2019ECP5046
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Yue GUAN
Waseda University
Takashi OHSAWA
Waseda University
Keyword
Latest Issue
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Yue GUAN, Takashi OHSAWA, "Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 11, pp. 685-692, November 2020, doi: 10.1587/transele.2019ECP5046.
Abstract: In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019ECP5046/_p
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@ARTICLE{e103-c_11_685,
author={Yue GUAN, Takashi OHSAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm},
year={2020},
volume={E103-C},
number={11},
pages={685-692},
abstract={In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.},
keywords={},
doi={10.1587/transele.2019ECP5046},
ISSN={1745-1353},
month={November},}
Copy
TY - JOUR
TI - Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm
T2 - IEICE TRANSACTIONS on Electronics
SP - 685
EP - 692
AU - Yue GUAN
AU - Takashi OHSAWA
PY - 2020
DO - 10.1587/transele.2019ECP5046
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2020
AB - In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.
ER -
English
