IEICE TRANSACTIONS on Electronics
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture
Summary :
In this paper, we describe a novel low-delay 4K 120-fps real-time HEVC decoder with a parallel processing architecture that conforms to the HEVC main 4:2:2 10 profile. It supports the hierarchical temporal scalable streams required for Ultra High Definition high-frame-rate broadcasting and also supports low-delay and high-bitrate decoding for video transmission uses. To achieve this support, the decoding processes are parallelized and pipelined at the frame level, slice level, and coding tree unit row level. The proposed decoder was implemented on three FPGAs operated at 133 and 150 MHz, and it achieved 300-Mbps stream decoding and 37-msec end-to-end delay with our concurrently developed 4K 120-fps encoder.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E103-C No.3 pp.77-84
- Publication Date
- 2020/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2019LHP0005
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
- Category
Authors
Ken NAKAMURA
NTT Media Intelligence Laboratories
Daisuke KOBAYASHI
NTT Media Intelligence Laboratories
Yuya OMORI
NTT Media Intelligence Laboratories
Tatsuya OSAWA
NTT Media Intelligence Laboratories
Takayuki ONISHI
NTT Media Intelligence Laboratories
Koyo NITTA
NTT Device Innovation Center
Hiroe IWASAKI
NTT Media Intelligence Laboratories
Keyword
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Ken NAKAMURA, Daisuke KOBAYASHI, Yuya OMORI, Tatsuya OSAWA, Takayuki ONISHI, Koyo NITTA, Hiroe IWASAKI, "Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 3, pp. 77-84, March 2020, doi: 10.1587/transele.2019LHP0005.
Abstract: In this paper, we describe a novel low-delay 4K 120-fps real-time HEVC decoder with a parallel processing architecture that conforms to the HEVC main 4:2:2 10 profile. It supports the hierarchical temporal scalable streams required for Ultra High Definition high-frame-rate broadcasting and also supports low-delay and high-bitrate decoding for video transmission uses. To achieve this support, the decoding processes are parallelized and pipelined at the frame level, slice level, and coding tree unit row level. The proposed decoder was implemented on three FPGAs operated at 133 and 150 MHz, and it achieved 300-Mbps stream decoding and 37-msec end-to-end delay with our concurrently developed 4K 120-fps encoder.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019LHP0005/_p
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@ARTICLE{e103-c_3_77,
author={Ken NAKAMURA, Daisuke KOBAYASHI, Yuya OMORI, Tatsuya OSAWA, Takayuki ONISHI, Koyo NITTA, Hiroe IWASAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture},
year={2020},
volume={E103-C},
number={3},
pages={77-84},
abstract={In this paper, we describe a novel low-delay 4K 120-fps real-time HEVC decoder with a parallel processing architecture that conforms to the HEVC main 4:2:2 10 profile. It supports the hierarchical temporal scalable streams required for Ultra High Definition high-frame-rate broadcasting and also supports low-delay and high-bitrate decoding for video transmission uses. To achieve this support, the decoding processes are parallelized and pipelined at the frame level, slice level, and coding tree unit row level. The proposed decoder was implemented on three FPGAs operated at 133 and 150 MHz, and it achieved 300-Mbps stream decoding and 37-msec end-to-end delay with our concurrently developed 4K 120-fps encoder.},
keywords={},
doi={10.1587/transele.2019LHP0005},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 77
EP - 84
AU - Ken NAKAMURA
AU - Daisuke KOBAYASHI
AU - Yuya OMORI
AU - Tatsuya OSAWA
AU - Takayuki ONISHI
AU - Koyo NITTA
AU - Hiroe IWASAKI
PY - 2020
DO - 10.1587/transele.2019LHP0005
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2020
AB - In this paper, we describe a novel low-delay 4K 120-fps real-time HEVC decoder with a parallel processing architecture that conforms to the HEVC main 4:2:2 10 profile. It supports the hierarchical temporal scalable streams required for Ultra High Definition high-frame-rate broadcasting and also supports low-delay and high-bitrate decoding for video transmission uses. To achieve this support, the decoding processes are parallelized and pipelined at the frame level, slice level, and coding tree unit row level. The proposed decoder was implemented on three FPGAs operated at 133 and 150 MHz, and it achieved 300-Mbps stream decoding and 37-msec end-to-end delay with our concurrently developed 4K 120-fps encoder.
ER -
English
