Design and Investigation of Silicon Gate-All-Around Junctionless Field-Effect Transistor Using a Step Thickness Gate Oxide

Wenlun ZHANG; Baokang WANG

doi:10.1587/transele.2020ECP5042

Design and Investigation of Silicon Gate-All-Around Junctionless Field-Effect Transistor Using a Step Thickness Gate Oxide

Wenlun ZHANG, Baokang WANG

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We design a silicon gate-all-around junctionless field-effect transistor (JLFET) using a step thickness gate oxide (GOX) by the Sentaurus technology computer-aided design simulation. We demonstrate the different gate-induced drain leakage (GIDL) mechanism of the traditional inversion-mode field-effect transistor (IMFET) and JLFET. The off leakage in the IMFET is dominated by the parasitic bipolar junction transistor effect, whereas in the JLFET it is a result of the volume conduction due to the screening effect of the accumulated holes. With the introduction of a 4 nm thick-second GOX and remaining first GOX thickness of 1 nm, the tunneling generation is reduced at the channel-drain interface, leading to a decrease in the off current of the JLFET. A thicker second GOX has the total gate capacitance of JLFETs, where a 0.3 ps improved intrinsic delay is achieved. This alleviates the capacitive load of the transistor in the circuit applications. Finally, the short-channel effects of the step thickness GOX JLFET were investigated with a total gate length from 40 nm to 6 nm. The results indicate that the step thickness GOX JLFETs perform better on the on/off ratio and drain-induced barrier lowering but exhibit a small degradation on the subthreshold swing and threshold roll-off.

Publication: IEICE TRANSACTIONS on Electronics Vol.E104-C No.8 pp.379-385

Publication Date: 2021/08/01

Publicized: 2021/01/15

Online ISSN: 1745-1353

DOI: 10.1587/transele.2020ECP5042

Type of Manuscript: PAPER

Category: Semiconductor Materials and Devices

Authors

Wenlun ZHANG
University of London (LSE),University of Colorado Boulder,Micron Technology, Inc.
Baokang WANG
Micron Technology, Inc.

Keyword

JLFET, TCAD, GIDL, BTBT, GAA transistor

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Wenlun ZHANG, Baokang WANG, "Design and Investigation of Silicon Gate-All-Around Junctionless Field-Effect Transistor Using a Step Thickness Gate Oxide" in IEICE TRANSACTIONS on Electronics, vol. E104-C, no. 8, pp. 379-385, August 2021, doi: 10.1587/transele.2020ECP5042.
Abstract: We design a silicon gate-all-around junctionless field-effect transistor (JLFET) using a step thickness gate oxide (GOX) by the Sentaurus technology computer-aided design simulation. We demonstrate the different gate-induced drain leakage (GIDL) mechanism of the traditional inversion-mode field-effect transistor (IMFET) and JLFET. The off leakage in the IMFET is dominated by the parasitic bipolar junction transistor effect, whereas in the JLFET it is a result of the volume conduction due to the screening effect of the accumulated holes. With the introduction of a 4 nm thick-second GOX and remaining first GOX thickness of 1 nm, the tunneling generation is reduced at the channel-drain interface, leading to a decrease in the off current of the JLFET. A thicker second GOX has the total gate capacitance of JLFETs, where a 0.3 ps improved intrinsic delay is achieved. This alleviates the capacitive load of the transistor in the circuit applications. Finally, the short-channel effects of the step thickness GOX JLFET were investigated with a total gate length from 40 nm to 6 nm. The results indicate that the step thickness GOX JLFETs perform better on the on/off ratio and drain-induced barrier lowering but exhibit a small degradation on the subthreshold swing and threshold roll-off.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020ECP5042/_p

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@ARTICLE{e104-c_8_379,
author={Wenlun ZHANG, Baokang WANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Investigation of Silicon Gate-All-Around Junctionless Field-Effect Transistor Using a Step Thickness Gate Oxide},
year={2021},
volume={E104-C},
number={8},
pages={379-385},
abstract={We design a silicon gate-all-around junctionless field-effect transistor (JLFET) using a step thickness gate oxide (GOX) by the Sentaurus technology computer-aided design simulation. We demonstrate the different gate-induced drain leakage (GIDL) mechanism of the traditional inversion-mode field-effect transistor (IMFET) and JLFET. The off leakage in the IMFET is dominated by the parasitic bipolar junction transistor effect, whereas in the JLFET it is a result of the volume conduction due to the screening effect of the accumulated holes. With the introduction of a 4 nm thick-second GOX and remaining first GOX thickness of 1 nm, the tunneling generation is reduced at the channel-drain interface, leading to a decrease in the off current of the JLFET. A thicker second GOX has the total gate capacitance of JLFETs, where a 0.3 ps improved intrinsic delay is achieved. This alleviates the capacitive load of the transistor in the circuit applications. Finally, the short-channel effects of the step thickness GOX JLFET were investigated with a total gate length from 40 nm to 6 nm. The results indicate that the step thickness GOX JLFETs perform better on the on/off ratio and drain-induced barrier lowering but exhibit a small degradation on the subthreshold swing and threshold roll-off.},
keywords={},
doi={10.1587/transele.2020ECP5042},
ISSN={1745-1353},
month={August},}

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TY - JOUR
TI - Design and Investigation of Silicon Gate-All-Around Junctionless Field-Effect Transistor Using a Step Thickness Gate Oxide
T2 - IEICE TRANSACTIONS on Electronics
SP - 379
EP - 385
AU - Wenlun ZHANG
AU - Baokang WANG
PY - 2021
DO - 10.1587/transele.2020ECP5042
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2021
AB - We design a silicon gate-all-around junctionless field-effect transistor (JLFET) using a step thickness gate oxide (GOX) by the Sentaurus technology computer-aided design simulation. We demonstrate the different gate-induced drain leakage (GIDL) mechanism of the traditional inversion-mode field-effect transistor (IMFET) and JLFET. The off leakage in the IMFET is dominated by the parasitic bipolar junction transistor effect, whereas in the JLFET it is a result of the volume conduction due to the screening effect of the accumulated holes. With the introduction of a 4 nm thick-second GOX and remaining first GOX thickness of 1 nm, the tunneling generation is reduced at the channel-drain interface, leading to a decrease in the off current of the JLFET. A thicker second GOX has the total gate capacitance of JLFETs, where a 0.3 ps improved intrinsic delay is achieved. This alleviates the capacitive load of the transistor in the circuit applications. Finally, the short-channel effects of the step thickness GOX JLFET were investigated with a total gate length from 40 nm to 6 nm. The results indicate that the step thickness GOX JLFETs perform better on the on/off ratio and drain-induced barrier lowering but exhibit a small degradation on the subthreshold swing and threshold roll-off.
ER -