We design a silicon gate-all-around junctionless field-effect transistor (JLFET) using a step thickness gate oxide (GOX) by the Sentaurus technology computer-aided design simulation. We demonstrate the different gate-induced drain leakage (GIDL) mechanism of the traditional inversion-mode field-effect transistor (IMFET) and JLFET. The off leakage in the IMFET is dominated by the parasitic bipolar junction transistor effect, whereas in the JLFET it is a result of the volume conduction due to the screening effect of the accumulated holes. With the introduction of a 4 nm thick-second GOX and remaining first GOX thickness of 1 nm, the tunneling generation is reduced at the channel-drain interface, leading to a decrease in the off current of the JLFET. A thicker second GOX has the total gate capacitance of JLFETs, where a 0.3 ps improved intrinsic delay is achieved. This alleviates the capacitive load of the transistor in the circuit applications. Finally, the short-channel effects of the step thickness GOX JLFET were investigated with a total gate length from 40 nm to 6 nm. The results indicate that the step thickness GOX JLFETs perform better on the on/off ratio and drain-induced barrier lowering but exhibit a small degradation on the subthreshold swing and threshold roll-off.

We discuss a new high performance computing service (HPCS) platform that has been developed to provide domain-neutral computing service under the governmental support from “EDucation-research Integration through Simulation On the Net” (EDISON) project. With a first focus on technical features, we not only present in-depth explanations of the implementation details, but also describe the strengths of the EDISON platform against the successful nanoHUB.org gateway. To validate the performance and utility of the platform, we provide benchmarking results for the resource virtualization framework, and prove the stability and promptness of the EDISON platform in processing simulation requests by analyzing several statistical datasets obtained from a three-month trial service in the initiative area of computational nanoelectronics. We firmly believe that this work provides a good opportunity for understanding the science gateway project ongoing for the first time in Republic of Korea, and that the technical details presented here can be served as an useful guideline for any potential designs of HPCS platforms.

Due to the increasing need for low-power circuits in mobile applications, numerous leakage and performance optimization techniques are being used in modern ICs. In the present paper, we propose a novel transistor-level technique to reduce leakage current while maintaining drive current. By slightly increasing the channel length at the edge of a device that exploits the edge effect, a leakage-optimized transistor can be produced. By using TCAD simulations, we analyze edge-length-biased transistors and then propose the optimal transistor shape for minimizing Ioff with the same or higher Ion current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits.

TCAD is gaining acceptance in the heterostructure industry. This article discusses the specific challenges a device simulator must manage to be a useful tool in designing and optimizing modern heterostructure devices. Example simulation results are given for HEMTs and HBTs, illustrating the complex physical processes in heterostructure devices, such as nonlocal effects in carrier transport, lattice self-heating, hot-electron effects, traps, electron tunneling, and quantum transport.

New physical models, algorithms, and parameters are needed to accurately model emerging silicon-on-insulator (SOI) devices. The modeling approaches for various emerging SOI technologies are discussed in this paper.

Interactions between ESD protection devices and other components of a chip can lead to complex and not easily anticipated discharge bevahior. Triggering of a protection MOSFET is equivalent to the closing of a fast switch and can cause substantial transient discharge currents. The peak value of this current depends on the chip capacitance, resistance, properties of the protection clamp, etc. Careful optimization of the protection circuit is therefore necessary to avoid current overstress and circuit failure.

The application of Technology CAD simulations for development of IC processes in foundry is presented. Examples include device design, Flash cell design and optical proximity correction for SRAM cell. The challenges of using TCAD tools in the IC foundry is also discussed.

TCAD (Technology Computer Aided Design) is the simulation of semiconductor processes and devices. Despite twenty years of development, there are still many TCAD skeptics. This paper will discuss some of the problems and limitations of TCAD, present some successful examples of its use, and discuss future simulation needs from a user's perspective. A key point is that the time pressures in modern semiconductor technology development often dictate the use of simple models for approximate results.

A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed. This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

Equipment simulation can provide valuable support in reactor design and process optimization. This article describes the physical and chemical models used in this technique and the current state of the art of the available software tools is reviewed. Moreover, the potential of equipment simulation will be highlighted by means of three recent examples from advanced quarter micron silicon process development. These include a vertical batch reactor for LPCVD of arsenic doped silicon oxide, a multi station tungsten CVD reactor, and a plasma reactor for silicon etching.

A new methodology for simulation-based CMOS process design has been proposed, using a Hierarchical Response Surface Method (HRSM) and an efficient experimental calibration. The design methodology has been verified using a 0.4 micron CMOS process. The proposed HRSM achieved a 60% reduction of process and device design cost in comparison with those of conventional TCAD. The procedure was performed in conjunction with an experimental calibration technique to provide a reliable threshold voltage prediction including process variation effects. The total CPU cost was 200 hr. on SUN SPARC 10 and the error of the predicted threshold voltage was less than 0.02 V.

In this paper, the formulation of unified transport model is reviewed along with its implementation in a three-dimensional device simulator. The model features an accurate description of the energy exchange among electrons, holes and lattice, and is therefore suitable for self-consistently simulating thermal effects and non-stationary phenomena, as well as their possible interactions. Despite the model complexity, it is shown that the computational effort required for its solution is reasonably close to more conventional approaches. Application examples are also given, in which both unipolar and bipolar devices are simulated, discussing the relative importance of different phenomena and highlighting the simultaneous occurrence of carrier and lattice heating.

In this paper, a "hydrodynamic" version of the three-dimensional code HFIELDS-3D is used to achieve a detailed knowledge on the distribution of the substrate current inside a recessed-oxide MOSFET. The physical model features a temperature-dependent formulation of the impact-ionization rate, allowing non-local effects to be accounted for. The discretization strategy relies on the Box Integration scheme and uses suitable generalizations of the Scharfetter-Gummel technique for the energy-balance equation. The simulation results show that the narrow-channel effect has a different impact on drain and substrate currents. Further three-dimensional effects, such as the extra heating of the carriers at the channel edge, are demonstrated.

A spherical-harmonics expansion method is used to find approximate numerical solutions of the Boltzmann Transport Equation in the homogeneous case. Acoustic and optical phonon scattering, ionized impurity scattering as well as an energy band structure fitting the silicon density of states up to 2.6 eV above the conduction-band edge are used in the model. Comparisons with Monte Carlo data show excellent agreement, and prove that detailed information on the high-energy tail of the distribution function can be obtained at very low cost using this methodology.