Design of Circuits and Packaging Systems for Security Chips

Makoto NAGATA

doi:10.1587/transele.2022CDI0001

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Design of Circuits and Packaging Systems for Security Chips

Makoto NAGATA

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Summary :

Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.

Publication: IEICE TRANSACTIONS on Electronics Vol.E106-C No.7 pp.345-351

Publication Date: 2023/07/01

Publicized: 2023/04/19

Online ISSN: 1745-1353

DOI: 10.1587/transele.2022CDI0001

Type of Manuscript: Special Section INVITED PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)

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Authors

Makoto NAGATA
Graduate School of Science, Technology and Innovation, Kobe University

Keyword

hardware security, secure packaging, cryptography, implementation attacks, side channel leakage, CMOS integrated circuits

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Makoto NAGATA, "Design of Circuits and Packaging Systems for Security Chips" in IEICE TRANSACTIONS on Electronics, vol. E106-C, no. 7, pp. 345-351, July 2023, doi: 10.1587/transele.2022CDI0001.
Abstract: Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CDI0001/_p

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@ARTICLE{e106-c_7_345,
author={Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Circuits and Packaging Systems for Security Chips},
year={2023},
volume={E106-C},
number={7},
pages={345-351},
abstract={Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.},
keywords={},
doi={10.1587/transele.2022CDI0001},
ISSN={1745-1353},
month={July},}

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TY - JOUR
TI - Design of Circuits and Packaging Systems for Security Chips
T2 - IEICE TRANSACTIONS on Electronics
SP - 345
EP - 351
AU - Makoto NAGATA
PY - 2023
DO - 10.1587/transele.2022CDI0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2023
AB - Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.
ER -