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IEICE TRANSACTIONS on Electronics

A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process

Haruki MARUOKA, Masashi HIFUMI, Jun FURUTA, Kazutoshi KOBAYASHI

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Summary :

We propose a radiation-hardened Flip-Flop (FF) with stacked transistors based on the Adaptive Coupling Flip-Flop (ACFF) with low power consumption in a 65 nm FDSOI process. The slave latch in ACFF is much weaker against soft errors than the master latch. We design several FFs with stacked transistors in the master or slave latches to mitigate soft errors. We investigate radiation hardness of the proposed FFs by α particle and neutron irradiation tests. The proposed FFs have higher radiation hardness than a conventional DFF and ACFF. Neutron irradiation and α particle tests revealed no error in the proposed AC Slave-Stacked FF (AC_SS FF) which has stacked transistors only in the slave latch. We also investigate radiation hardness of the proposed FFs by heavy ion irradiation. The proposed FFs maintain higher radiation hardness up to 40 MeV-cm2/mg than the conventional DFF. Stacked inverters become more sensitive to soft errors by increasing tilt angles. AC_SS FF achieves higher radiation hardness than ACFF with the performance equivalent to that of ACFF.

Publication
IEICE TRANSACTIONS on Electronics Vol.E101-C No.4 pp.273-280
Publication Date
2018/04/01
Publicized
Online ISSN
1745-1353
DOI
10.1587/transele.E101.C.273
Type of Manuscript
Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category

Authors

Haruki MARUOKA
  Kyoto Institute of Technology
Masashi HIFUMI
  Kyoto Institute of Technology
Jun FURUTA
  Kyoto Institute of Technology
Kazutoshi KOBAYASHI
  Kyoto Institute of Technology

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