We propose a sampling method that incorporates a normally distributed sampling series for EEG measurements using compressed sensing. We confirmed that the ADC sampling count and amount of wirelessly transmitted data can be reduced by 11% while maintaining a reconstruction accuracy similar to that of the conventional method.

In this paper, we propose an IEEE 802.15.10-based layer 2 routing (L2R) method with a load balancing algorithm; the proposal considers fairness in terms of the cumulative number of sending packets at each terminal to resolve the packet concentration problem for the IEEE 802.15.4-based low-power consumption wireless smart utility network (Wi-SUN) systems. The proposal uses the accumulated sending times of each terminal as a weight in calculating each path quality metric (PQM) to decide multi-hopping routes with load balancing in the network. Computer simulation of the mesh network with 256 terminals shows that the proposed routing method can improve the maximum sending ratio (MSR), defined as the ratio of the maximum sending times to the average number of sending times in the network, by 56% with no degradation of the end-to-end communication success ratio (E2E-SR). The proposed algorithm is also experimentally evaluated by using actual Wi-SUN modules. The proposed routing method also improves the MSR by 84% with 70 terminals. Computer simulations and experiments prove the effectiveness of the proposed method in terms of load balancing.

We propose a radiation-hardened Flip-Flop (FF) with stacked transistors based on the Adaptive Coupling Flip-Flop (ACFF) with low power consumption in a 65 nm FDSOI process. The slave latch in ACFF is much weaker against soft errors than the master latch. We design several FFs with stacked transistors in the master or slave latches to mitigate soft errors. We investigate radiation hardness of the proposed FFs by α particle and neutron irradiation tests. The proposed FFs have higher radiation hardness than a conventional DFF and ACFF. Neutron irradiation and α particle tests revealed no error in the proposed AC Slave-Stacked FF (AC_SS FF) which has stacked transistors only in the slave latch. We also investigate radiation hardness of the proposed FFs by heavy ion irradiation. The proposed FFs maintain higher radiation hardness up to 40 MeV-cm2/mg than the conventional DFF. Stacked inverters become more sensitive to soft errors by increasing tilt angles. AC_SS FF achieves higher radiation hardness than ACFF with the performance equivalent to that of ACFF.

This paper proposes a technique for two-stage operational amplifiers (OPAMPs) to optimize power consumption according to various channel conditions of wireless communication systems. The proposed OPAMP has the ability of reducing the quiescent current of each stage independently by introducing additional common-mode feedback, therefore more optimization is possible according to the channel conditions than conventional two-stage OPAMPs. The simulations verify the benefits of the technique. As a proof-of-concept topology, the proposed OPAMPs were used in a channel-selection filter for a multi-standard mobile-TV receiver. The power consumption of the filter, 3.4–5.0 mW, was adjustable according to the bandwidth, the noise, and the jammer level. The performance of the filter meets the requirements and verifies the effectiveness of the proposed approach. The filter was fabricated in 0.18-µm CMOS and occupied 0.64 mm2.

This paper describes the evaluation of the Voltage Down Converter (VDC) with low ratio of consuming current to load current in DC/AC operation mode. The stability, response and power consumption are investigated. First, for the stability and response, the VDC can operate in the condition that the bounce of the down voltage (dVDL) is no more than 10% of the setting voltage and the maximum load operation frequency (fmax) is 100 MHz at the average load current 70 mA (the maximum load current 140 mA). Secondly, for the power consumption, by using this VDC technology, the value of IC/IL can be suppressed to 5.1E-4 (IC: total consuming current in VDC, IL: average load current) in the condition that dVDL is no more than 10% of the setting voltage and fmax is 10 MHz at the average load current 70 mA. Thus, it is made clear that the VDC can realize high stability, good response and low power consumption at the same time. This technology is suitable for high performance ULSIs which require large load current and low-power consumption.

Low-power technology for front-end GaAs ICs and hybrid IC (HIC) for a mobile communication equipment will be presented. For low-power operation of GaAs front-end ICs, new techniques of the intermediate tuned circuits, the single-ended mixer, dualgate MESFETs, and the asymmetric self-aligned LDD process were investigated. The designed down-converter IC showed conversion gain of 21 dB, noise figure of 3.5 dB, 3rd-order intercept point in output level (IP3out) of 4.0 dBm, image-rejection ratio of 20 dB at 880 MHz, operating at 3.0 V of supply voltage and 5.0 mA of dissipation current. The down-converter IC was also designed for 1.9 GHz to obtain conversion gain of 20 dB, noise figure of 4.0 dB, IP3out of 4.0 dBm, image-rejection ratio of 20 dB at 3.0 V, 5.0 mA. The up-converter IC was designed for 1.9 GHz using the same topology of circuit and showed conversion gain of 15 dB, IP3out of 7.5 dBm, and 1 dB compression level of -8 dBm with -20 dBm of LO input power, operating at 3.0 V, 8.0 mA. Another approach to the low-power operation was carried out by HIC using the GaAs down-converter IC chip. The HIC was designed for 880 MHz to show conversion gain of 27 dB, noise figure of 3.3 dB, IP3out of 3.0 dBm, image-rejection ratio of 12 dB, at 2.7 V, 4.5 mA. The HIC measures only 8.0 mm6.0 mm1.2 mm.