IEICE TRANSACTIONS on Electronics
Open Access
Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing
-
Full Text Views
27
- Cite this
- Free PDF (1.3MB)
Summary :
CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E101-C No.5 pp.359-369
- Publication Date
- 2018/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E101.C.359
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Innovative Superconducting Devices Based on New Physical Phenomena)
- Category
Authors
Koki ISHIDA
Kyushu University
Masamitsu TANAKA
Nagoya University
Takatsugu ONO
Kyushu University
Koji INOUE
Kyushu University
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Koki ISHIDA, Masamitsu TANAKA, Takatsugu ONO, Koji INOUE, "Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing" in IEICE TRANSACTIONS on Electronics,
vol. E101-C, no. 5, pp. 359-369, May 2018, doi: 10.1587/transele.E101.C.359.
Abstract: CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.359/_p
Copy
@ARTICLE{e101-c_5_359,
author={Koki ISHIDA, Masamitsu TANAKA, Takatsugu ONO, Koji INOUE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing},
year={2018},
volume={E101-C},
number={5},
pages={359-369},
abstract={CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.},
keywords={},
doi={10.1587/transele.E101.C.359},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing
T2 - IEICE TRANSACTIONS on Electronics
SP - 359
EP - 369
AU - Koki ISHIDA
AU - Masamitsu TANAKA
AU - Takatsugu ONO
AU - Koji INOUE
PY - 2018
DO - 10.1587/transele.E101.C.359
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2018
AB - CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.
ER -
English
