A Dynamic Latched Comparator Using Area-Efficient Stochastic Offset Voltage Detection Technique
Summary :
This paper presents a self-calibrating dynamic latched comparator with a stochastic offset voltage detector that can be realized by using simple digital circuitry. An offset voltage of the comparator is compensated by using a statistical calibration scheme, and the offset voltage detector uses the uncertainty in the comparator output. Thanks to the simple offset detection technique, all the calibration circuitry can be synthesized using only standard logic cells. This paper also gives a design methodology that can provide the optimal design parameters for the detector on the basis of fundamental statistics, and the correctness of the design methodology was statistically validated through measurement. The proposed self-calibrating comparator system was fabricated in a 180 nm 1P6M CMOS process. The prototype achieved a 38 times improvement in the three-sigma of the offset voltage from 6.01 mV to 158 µV.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E101-C No.5 pp.396-403
- Publication Date
- 2018/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E101.C.396
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Takayuki OKAZAWA
Toyohashi University of Technology
Ippei AKITA
Toyohashi University of Technology
Keyword
Latest Issue
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Takayuki OKAZAWA, Ippei AKITA, "A Dynamic Latched Comparator Using Area-Efficient Stochastic Offset Voltage Detection Technique" in IEICE TRANSACTIONS on Electronics,
vol. E101-C, no. 5, pp. 396-403, May 2018, doi: 10.1587/transele.E101.C.396.
Abstract: This paper presents a self-calibrating dynamic latched comparator with a stochastic offset voltage detector that can be realized by using simple digital circuitry. An offset voltage of the comparator is compensated by using a statistical calibration scheme, and the offset voltage detector uses the uncertainty in the comparator output. Thanks to the simple offset detection technique, all the calibration circuitry can be synthesized using only standard logic cells. This paper also gives a design methodology that can provide the optimal design parameters for the detector on the basis of fundamental statistics, and the correctness of the design methodology was statistically validated through measurement. The proposed self-calibrating comparator system was fabricated in a 180 nm 1P6M CMOS process. The prototype achieved a 38 times improvement in the three-sigma of the offset voltage from 6.01 mV to 158 µV.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.396/_p
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@ARTICLE{e101-c_5_396,
author={Takayuki OKAZAWA, Ippei AKITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Dynamic Latched Comparator Using Area-Efficient Stochastic Offset Voltage Detection Technique},
year={2018},
volume={E101-C},
number={5},
pages={396-403},
abstract={This paper presents a self-calibrating dynamic latched comparator with a stochastic offset voltage detector that can be realized by using simple digital circuitry. An offset voltage of the comparator is compensated by using a statistical calibration scheme, and the offset voltage detector uses the uncertainty in the comparator output. Thanks to the simple offset detection technique, all the calibration circuitry can be synthesized using only standard logic cells. This paper also gives a design methodology that can provide the optimal design parameters for the detector on the basis of fundamental statistics, and the correctness of the design methodology was statistically validated through measurement. The proposed self-calibrating comparator system was fabricated in a 180 nm 1P6M CMOS process. The prototype achieved a 38 times improvement in the three-sigma of the offset voltage from 6.01 mV to 158 µV.},
keywords={},
doi={10.1587/transele.E101.C.396},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - A Dynamic Latched Comparator Using Area-Efficient Stochastic Offset Voltage Detection Technique
T2 - IEICE TRANSACTIONS on Electronics
SP - 396
EP - 403
AU - Takayuki OKAZAWA
AU - Ippei AKITA
PY - 2018
DO - 10.1587/transele.E101.C.396
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2018
AB - This paper presents a self-calibrating dynamic latched comparator with a stochastic offset voltage detector that can be realized by using simple digital circuitry. An offset voltage of the comparator is compensated by using a statistical calibration scheme, and the offset voltage detector uses the uncertainty in the comparator output. Thanks to the simple offset detection technique, all the calibration circuitry can be synthesized using only standard logic cells. This paper also gives a design methodology that can provide the optimal design parameters for the detector on the basis of fundamental statistics, and the correctness of the design methodology was statistically validated through measurement. The proposed self-calibrating comparator system was fabricated in a 180 nm 1P6M CMOS process. The prototype achieved a 38 times improvement in the three-sigma of the offset voltage from 6.01 mV to 158 µV.
ER -
English
