Effects of Address-on-Time on Wall Voltage Variation during Address-Period in AC Plasma Display Panel
Summary :
To explain the variation of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the address-on-time by using the Vt closed curves. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the address-on-time. It was also observed that the wall voltage variation during an address period strongly depended on the voltage difference between the scan and address electrodes. Based on this result, the modified driving waveform to raise the level of Vscanw, was proposed to minimize the voltage difference between the scan and address electrodes. However, the modified driving waveform resulted in the increase in the falling time of scan pulse. Finally, the overlapped double scan waveform was proposed to reduce a falling time of scan pulse under the raised voltage level of Vscanw, also.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.11 pp.1347-1352
- Publication Date
- 2009/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.1347
- Type of Manuscript
- Special Section PAPER (Special Section on Electronic Displays)
- Category
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Byung-Tae CHOI, Hyung Dal PARK, Heung-Sik TAE, "Effects of Address-on-Time on Wall Voltage Variation during Address-Period in AC Plasma Display Panel" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 11, pp. 1347-1352, November 2009, doi: 10.1587/transele.E92.C.1347.
Abstract: To explain the variation of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the address-on-time by using the Vt closed curves. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the address-on-time. It was also observed that the wall voltage variation during an address period strongly depended on the voltage difference between the scan and address electrodes. Based on this result, the modified driving waveform to raise the level of Vscanw, was proposed to minimize the voltage difference between the scan and address electrodes. However, the modified driving waveform resulted in the increase in the falling time of scan pulse. Finally, the overlapped double scan waveform was proposed to reduce a falling time of scan pulse under the raised voltage level of Vscanw, also.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1347/_p
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@ARTICLE{e92-c_11_1347,
author={Byung-Tae CHOI, Hyung Dal PARK, Heung-Sik TAE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Effects of Address-on-Time on Wall Voltage Variation during Address-Period in AC Plasma Display Panel},
year={2009},
volume={E92-C},
number={11},
pages={1347-1352},
abstract={To explain the variation of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the address-on-time by using the Vt closed curves. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the address-on-time. It was also observed that the wall voltage variation during an address period strongly depended on the voltage difference between the scan and address electrodes. Based on this result, the modified driving waveform to raise the level of Vscanw, was proposed to minimize the voltage difference between the scan and address electrodes. However, the modified driving waveform resulted in the increase in the falling time of scan pulse. Finally, the overlapped double scan waveform was proposed to reduce a falling time of scan pulse under the raised voltage level of Vscanw, also.},
keywords={},
doi={10.1587/transele.E92.C.1347},
ISSN={1745-1353},
month={November},}
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TY - JOUR
TI - Effects of Address-on-Time on Wall Voltage Variation during Address-Period in AC Plasma Display Panel
T2 - IEICE TRANSACTIONS on Electronics
SP - 1347
EP - 1352
AU - Byung-Tae CHOI
AU - Hyung Dal PARK
AU - Heung-Sik TAE
PY - 2009
DO - 10.1587/transele.E92.C.1347
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2009
AB - To explain the variation of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the address-on-time by using the Vt closed curves. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the address-on-time. It was also observed that the wall voltage variation during an address period strongly depended on the voltage difference between the scan and address electrodes. Based on this result, the modified driving waveform to raise the level of Vscanw, was proposed to minimize the voltage difference between the scan and address electrodes. However, the modified driving waveform resulted in the increase in the falling time of scan pulse. Finally, the overlapped double scan waveform was proposed to reduce a falling time of scan pulse under the raised voltage level of Vscanw, also.
ER -
English
