Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
Summary :
An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.3 pp.341-351
- Publication Date
- 2009/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.341
- Type of Manuscript
- PAPER
- Category
- Electronic Components
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Keyword
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Ming-Dou KER, Yuan-Wen HSIAO, "Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 3, pp. 341-351, March 2009, doi: 10.1587/transele.E92.C.341.
Abstract: An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.341/_p
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@ARTICLE{e92-c_3_341,
author={Ming-Dou KER, Yuan-Wen HSIAO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits},
year={2009},
volume={E92-C},
number={3},
pages={341-351},
abstract={An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.},
keywords={},
doi={10.1587/transele.E92.C.341},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 341
EP - 351
AU - Ming-Dou KER
AU - Yuan-Wen HSIAO
PY - 2009
DO - 10.1587/transele.E92.C.341
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2009
AB - An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.
ER -
English
