High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer

Yu-Lung LO; Wei-Bin YANG; Ting-Sheng CHAO; Kuo-Hsing CHENG

doi:10.1587/transele.E92.C.890

High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer

Yu-Lung LO, Wei-Bin YANG, Ting-Sheng CHAO, Kuo-Hsing CHENG

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A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E92-C No.6 pp.890-893

Publication Date: 2009/06/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E92.C.890

Type of Manuscript: LETTER

Category: Electronic Circuits

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Yu-Lung LO, Wei-Bin YANG, Ting-Sheng CHAO, Kuo-Hsing CHENG, "High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer" in IEICE TRANSACTIONS on Electronics, vol. E92-C, no. 6, pp. 890-893, June 2009, doi: 10.1587/transele.E92.C.890.
Abstract: A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.890/_p

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@ARTICLE{e92-c_6_890,
author={Yu-Lung LO, Wei-Bin YANG, Ting-Sheng CHAO, Kuo-Hsing CHENG, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer},
year={2009},
volume={E92-C},
number={6},
pages={890-893},
abstract={A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.},
keywords={},
doi={10.1587/transele.E92.C.890},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
T2 - IEICE TRANSACTIONS on Electronics
SP - 890
EP - 893
AU - Yu-Lung LO
AU - Wei-Bin YANG
AU - Ting-Sheng CHAO
AU - Kuo-Hsing CHENG
PY - 2009
DO - 10.1587/transele.E92.C.890
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.
ER -