IEICE TRANSACTIONS on Electronics
Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm
Summary :
To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.3 pp.279-287
- Publication Date
- 2010/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.279
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
- Category
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Qingsheng HU, Hua-An ZHAO, "Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 279-287, March 2010, doi: 10.1587/transele.E93.C.279.
Abstract: To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.279/_p
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@ARTICLE{e93-c_3_279,
author={Qingsheng HU, Hua-An ZHAO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm},
year={2010},
volume={E93-C},
number={3},
pages={279-287},
abstract={To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64
keywords={},
doi={10.1587/transele.E93.C.279},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm
T2 - IEICE TRANSACTIONS on Electronics
SP - 279
EP - 287
AU - Qingsheng HU
AU - Hua-An ZHAO
PY - 2010
DO - 10.1587/transele.E93.C.279
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64
ER -
English
