A W-graph is a partially known graph which contains wild-components. A wild-component is an incompletely defined connected subgraph having p vertices and p-1 unspecified edges. The informations we know on a wild-component are which has a vertex set and between any two vertices there is one and only one path. In this paper, we discuss the properties of circuits in a W-graph (called W-circuits). Although a W-graph has unspecified edges, we can obtain some important properties of W-circuits. We show that the W-ring sum of W-circuits is also a W-circuit in the same W-graph. The following (1) and (2) are proved: (1) A W-circuit Ci of a W-graph can be transformed into either a circuit or an edge disjoint union of circuits, denoted by Ci*, of a graph derived from the W-graph, (2) if W-circuits C1, C2, , Cn are linearly independent, then C1*, C2*, , Cn* obtained in (1) are also linearly independent.

Cooperative wireless communication is a communication mechanism to attain diversity through virtual antenna array that is formed by sharing resources among different users. Different strategies of resource utilization such as amplify-and-forward (AF) and decode-and-forward (DF) already exist in cooperative networks. Although the implementation of these strategies is simple, their utilization of the channel state information (CSI) is generally poor. As a result, the outage and bit error rate (BER) performances need much more improvement in order to satisfy the upcoming high data rate demands. For that to happen the spectral efficiency supported by a wireless system at a very low outage probability should be increased. In this paper a new approach, based on the previously existing ones, called CSI directed estimate and forward (CDEF) with a reduced estimation domain is proposed. A closed form solution for the optimal signal estimation at the relay using minimum mean square error (MMSE) as well as a possible set reduction of the estimation domain is given. It will be shown that this new strategy attains better symbol error rate (SER) and outage performance than AF or DF when the source relay link is comparatively better than the relay destination link. Simulation results also show that it has got better spectral efficiency at low outage probability for a given signal to noise ratio (SNR) as well as for a fixed outage probability in any operating SNR range.

This paper presents a joint linear processing scheme for two-hop and half-duplex distributed amplify-and-forward (AF) relaying networks with one source, one destination and multiple relays, each having multiple antennas. By using the minimum mean-square error (MMSE) criterion and the Wiener filter principle, the joint relay and destination design with perfect channel state information (CSI) is first formulated as an optimization problem with respect to the relay precoding matrix under the constraint of a total relay transmit power. The constrained optimization with an objective to design the relay block-diagonal matrix is then simplified to an equivalent problem with scalar optimization variables. Next, it is revealed that the scalar-version optimization is convex when the total relay power or the second-hop SNR (signal to noise ratio) is above a certain threshold. The underlying optimization problem, which is non-convex in general, is solved by complementary geometric programming (CGP). The proposed joint relay and destination design with perfect CSI is also extended for practical systems where only the channel mean and covariance matrix are available, leading to a robust processing scheme. Finally, Monte Carlo simulations are undertaken to demonstrate the superior MSE (mean-square error) and SER (symbol error rate) performances of the proposed scheme over the existing relaying method in the case of relatively large second-hop SNR.

We will introduce W-trees of a W-graph which is a graph containing wild components. A wild component is an incompletely defined subgraph which is known to be a tree but what kind of the tree is unspecified. W-tree is defined as a set of edges and vertices of wild components obtained from a non-sigular major submatrix of a W-incidence matrix. The properties of a W-tree are useful for studying linear independent W-cutsets and so on in a W-graph.

This paper proposes a new family of space-time block codes whose transmission rate is 1 symbol per channel use. The proposed space-time codes can achieve full transmit diversity with larger coding gain for the constellation carved from the scaled complex integer ring κZ[i]. It is confirmed that the performances of the proposed space-time codes are superior to the existing space-time block codes by our simulation results.

This paper considers the power allocation (PA) problem for three-node decode-and-forward (DF) relay communication systems, where the aggregate transmit power constraint is imposed on the source and the relay and the optimization target is to maximize the system's instantaneous information rate. Since the relay is equipped with multiple antennas, the receiver and transmitter beamforming strategies are generally adopted. In this paper, we start by proposing a closed-form solution for the frequency-flat (FF) fading environment, then give a bisection algorithm with low complexity to obtain an optimal solution for the frequency-selective (FS) fading scenario. Finally, simulations validate the proposed methods.

A floorplan specifies the layout of modules in very large scale integration (VLSI) design, and a new code, called the EQ-sequence, for representing a floorplan is presented in this paper. The EQ-sequence is based on a Q-sequence. The EQ-sequence can preserve the adjacent relationships of rooms on a floorplan, but the Q-sequence cannot. The algorithms for encoding, moving and decoding of an EQ-sequence are introduced. With the EQ-sequence, we can check whether two modules abut each other on a floorplan. It has been proved that any floorplan of n rooms is uniquely encoded by an EQ-sequence and any EQ-sequence is uniquely decoded to a floorplan, both in O(n) time.

To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64 64 FSSA using FSSA_DI algorithm is implemented by four Xilinx Vertex-4 FPGAs. Measurement results show that the data rates of our solution can be up to 800 Mbps and the tradeoff between performance and hardware complexity has been solved peacefully.

A new approach for topological routing is proposed by W-graph. We employ a W-graph Gw(V, E, W) for indicating all nets which will be assigned to two-layer, where V is a set of all terminals, E is a set of edges corresponding to two-terminal nets and W is a set of wild components corresponding to multi-terminal nets. Such that the topological routing problem can be considered as: Given a circle H containing V in the sequence corresponding to terminals on the boundary of routing region, then drawing H Gw on a plane with minimum number of created vertices (crossing points on H).