IEICE TRANSACTIONS on Electronics
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
Summary :
According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a "BISER" (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.3 pp.340-346
- Publication Date
- 2010/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.340
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Jun FURUTA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, "An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 340-346, March 2010, doi: 10.1587/transele.E93.C.340.
Abstract: According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a "BISER" (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.340/_p
Copy
@ARTICLE{e93-c_3_340,
author={Jun FURUTA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity},
year={2010},
volume={E93-C},
number={3},
pages={340-346},
abstract={According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a "BISER" (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.},
keywords={},
doi={10.1587/transele.E93.C.340},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
T2 - IEICE TRANSACTIONS on Electronics
SP - 340
EP - 346
AU - Jun FURUTA
AU - Kazutoshi KOBAYASHI
AU - Hidetoshi ONODERA
PY - 2010
DO - 10.1587/transele.E93.C.340
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a "BISER" (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.
ER -
English
