On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques

Chia-Yi LIN; Li-Chung HSU; Hung-Ming CHEN

doi:10.1587/transele.E93.C.369

On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques

Chia-Yi LIN, Li-Chung HSU, Hung-Ming CHEN

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With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful planning in Design For Testability (DFT) design, circuits consume more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present two approaches to minimize scan based DFT power dissipation. First methodology includes routing cost consideration in scan chain reordering after cell placement, while second methodology provides test pattern compression for lower power. We formulate the first problem as a Traveling Salesman Problem (TSP), with different cost evaluation from, and apply an efficient heuristic to solve it. In the second problem, we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation. The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in . The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks. We also provide the integration flow of these two approaches in this paper.

Publication: IEICE TRANSACTIONS on Electronics Vol.E93-C No.3 pp.369-378

Publication Date: 2010/03/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E93.C.369

Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)

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Chia-Yi LIN, Li-Chung HSU, Hung-Ming CHEN, "On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques" in IEICE TRANSACTIONS on Electronics, vol. E93-C, no. 3, pp. 369-378, March 2010, doi: 10.1587/transele.E93.C.369.
Abstract: With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful planning in Design For Testability (DFT) design, circuits consume more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present two approaches to minimize scan based DFT power dissipation. First methodology includes routing cost consideration in scan chain reordering after cell placement, while second methodology provides test pattern compression for lower power. We formulate the first problem as a Traveling Salesman Problem (TSP), with different cost evaluation from, and apply an efficient heuristic to solve it. In the second problem, we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation. The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in . The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks. We also provide the integration flow of these two approaches in this paper.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.369/_p

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@ARTICLE{e93-c_3_369,
author={Chia-Yi LIN, Li-Chung HSU, Hung-Ming CHEN, },
journal={IEICE TRANSACTIONS on Electronics},
title={On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques},
year={2010},
volume={E93-C},
number={3},
pages={369-378},
abstract={With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful planning in Design For Testability (DFT) design, circuits consume more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present two approaches to minimize scan based DFT power dissipation. First methodology includes routing cost consideration in scan chain reordering after cell placement, while second methodology provides test pattern compression for lower power. We formulate the first problem as a Traveling Salesman Problem (TSP), with different cost evaluation from, and apply an efficient heuristic to solve it. In the second problem, we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation. The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in . The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks. We also provide the integration flow of these two approaches in this paper.},
keywords={},
doi={10.1587/transele.E93.C.369},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques
T2 - IEICE TRANSACTIONS on Electronics
SP - 369
EP - 378
AU - Chia-Yi LIN
AU - Li-Chung HSU
AU - Hung-Ming CHEN
PY - 2010
DO - 10.1587/transele.E93.C.369
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful planning in Design For Testability (DFT) design, circuits consume more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present two approaches to minimize scan based DFT power dissipation. First methodology includes routing cost consideration in scan chain reordering after cell placement, while second methodology provides test pattern compression for lower power. We formulate the first problem as a Traveling Salesman Problem (TSP), with different cost evaluation from, and apply an efficient heuristic to solve it. In the second problem, we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation. The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in . The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks. We also provide the integration flow of these two approaches in this paper.
ER -