With the advancement of VLSI manufacturing technology, entire electronic systems can be implemented in a single integrated circuit. Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful planning in Design For Testability (DFT) design, circuits consume more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present two approaches to minimize scan based DFT power dissipation. First methodology includes routing cost consideration in scan chain reordering after cell placement, while second methodology provides test pattern compression for lower power. We formulate the first problem as a Traveling Salesman Problem (TSP), with different cost evaluation from, and apply an efficient heuristic to solve it. In the second problem, we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation. The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in . The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks. We also provide the integration flow of these two approaches in this paper.

In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a novel processing order with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to the software implementation. Moreover, the system performance of our design significantly outperforms the previous proposals.