A bootstrapped analog switch with constant on-resistance is proposed for the successive approximation (SA) analog-to-digital converters (ADCs) that have many input-sampling switches. The initialization circuit, which is composed of a short pulse generator and a transmission gate, improves the linearity of the proposed bootstrapped analog switch by reducing the effect of the capacitive load. To evaluate the proposed bootstrapped analog switch, the 10-bit 1 MS/s CMOS SA ADC with a rail-to-rail differential input signal was designed by using a 0.18 µm CMOS process with 1.0 V supply voltage. The proposed bootstrapped analog switch reduced the maximum VGS variation of the conventional bootstrapped analog switch by 67%. It also enhanced the signal to noise-distortion ratio of the SA ADC by 4.8 dB when the capacitance of its gate node is 100 fF, and this improvement was maximized when the capacitance of its gate node increases.
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Sang-hun KIM, Yong-Hwan LEE, Hoon-Ju CHUNG, Young-Chan JANG, "A Bootstrapped Analog Switch with Constant On-Resistance" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 6, pp. 1069-1071, June 2011, doi: 10.1587/transele.E94.C.1069.
Abstract: A bootstrapped analog switch with constant on-resistance is proposed for the successive approximation (SA) analog-to-digital converters (ADCs) that have many input-sampling switches. The initialization circuit, which is composed of a short pulse generator and a transmission gate, improves the linearity of the proposed bootstrapped analog switch by reducing the effect of the capacitive load. To evaluate the proposed bootstrapped analog switch, the 10-bit 1 MS/s CMOS SA ADC with a rail-to-rail differential input signal was designed by using a 0.18 µm CMOS process with 1.0 V supply voltage. The proposed bootstrapped analog switch reduced the maximum VGS variation of the conventional bootstrapped analog switch by 67%. It also enhanced the signal to noise-distortion ratio of the SA ADC by 4.8 dB when the capacitance of its gate node is 100 fF, and this improvement was maximized when the capacitance of its gate node increases.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1069/_p
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@ARTICLE{e94-c_6_1069,
author={Sang-hun KIM, Yong-Hwan LEE, Hoon-Ju CHUNG, Young-Chan JANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Bootstrapped Analog Switch with Constant On-Resistance},
year={2011},
volume={E94-C},
number={6},
pages={1069-1071},
abstract={A bootstrapped analog switch with constant on-resistance is proposed for the successive approximation (SA) analog-to-digital converters (ADCs) that have many input-sampling switches. The initialization circuit, which is composed of a short pulse generator and a transmission gate, improves the linearity of the proposed bootstrapped analog switch by reducing the effect of the capacitive load. To evaluate the proposed bootstrapped analog switch, the 10-bit 1 MS/s CMOS SA ADC with a rail-to-rail differential input signal was designed by using a 0.18 µm CMOS process with 1.0 V supply voltage. The proposed bootstrapped analog switch reduced the maximum VGS variation of the conventional bootstrapped analog switch by 67%. It also enhanced the signal to noise-distortion ratio of the SA ADC by 4.8 dB when the capacitance of its gate node is 100 fF, and this improvement was maximized when the capacitance of its gate node increases.},
keywords={},
doi={10.1587/transele.E94.C.1069},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - A Bootstrapped Analog Switch with Constant On-Resistance
T2 - IEICE TRANSACTIONS on Electronics
SP - 1069
EP - 1071
AU - Sang-hun KIM
AU - Yong-Hwan LEE
AU - Hoon-Ju CHUNG
AU - Young-Chan JANG
PY - 2011
DO - 10.1587/transele.E94.C.1069
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2011
AB - A bootstrapped analog switch with constant on-resistance is proposed for the successive approximation (SA) analog-to-digital converters (ADCs) that have many input-sampling switches. The initialization circuit, which is composed of a short pulse generator and a transmission gate, improves the linearity of the proposed bootstrapped analog switch by reducing the effect of the capacitive load. To evaluate the proposed bootstrapped analog switch, the 10-bit 1 MS/s CMOS SA ADC with a rail-to-rail differential input signal was designed by using a 0.18 µm CMOS process with 1.0 V supply voltage. The proposed bootstrapped analog switch reduced the maximum VGS variation of the conventional bootstrapped analog switch by 67%. It also enhanced the signal to noise-distortion ratio of the SA ADC by 4.8 dB when the capacitance of its gate node is 100 fF, and this improvement was maximized when the capacitance of its gate node increases.
ER -