One of the most difficult problems that remains to be solved in wire interconnect architectures is the achievement of lower latency and higher concurrency on a shared bus or link without increasing the power and circuit overhead. Novel improvements in short distance on- and off-chip interconnects can be provided by using a multi-band RF interconnect (RF-I) system. Unlike the conventional current- or voltage-mode square wave signaling transceivers that use binary or multilevel baseband signals, the proposed RF-I transceiver uses high-frequency modulated RF passband signals with binary phase-shift keying (BPSK) modulation. The proposed low-overhead RF-I transceiver using 0.18-µm CMOS technology achieves an aggregate data rate of 4 Gb/s/pin between four I/Os (2Tx-to-2Rx) on a shared FR4 PCB line using two carriers of 6 GHz and 12 GHz. The two transceivers occupy an area of 0.077 mm2 and dissipate a power of about 25 mW with a power efficiency of 6.25 pJ/bit.
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Jongsun KIM, Gyungsu BYUN, M. Frank CHANG, "A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 5, pp. 854-857, May 2011, doi: 10.1587/transele.E94.C.854.
Abstract: One of the most difficult problems that remains to be solved in wire interconnect architectures is the achievement of lower latency and higher concurrency on a shared bus or link without increasing the power and circuit overhead. Novel improvements in short distance on- and off-chip interconnects can be provided by using a multi-band RF interconnect (RF-I) system. Unlike the conventional current- or voltage-mode square wave signaling transceivers that use binary or multilevel baseband signals, the proposed RF-I transceiver uses high-frequency modulated RF passband signals with binary phase-shift keying (BPSK) modulation. The proposed low-overhead RF-I transceiver using 0.18-µm CMOS technology achieves an aggregate data rate of 4 Gb/s/pin between four I/Os (2Tx-to-2Rx) on a shared FR4 PCB line using two carriers of 6 GHz and 12 GHz. The two transceivers occupy an area of 0.077 mm2 and dissipate a power of about 25 mW with a power efficiency of 6.25 pJ/bit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.854/_p
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@ARTICLE{e94-c_5_854,
author={Jongsun KIM, Gyungsu BYUN, M. Frank CHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects},
year={2011},
volume={E94-C},
number={5},
pages={854-857},
abstract={One of the most difficult problems that remains to be solved in wire interconnect architectures is the achievement of lower latency and higher concurrency on a shared bus or link without increasing the power and circuit overhead. Novel improvements in short distance on- and off-chip interconnects can be provided by using a multi-band RF interconnect (RF-I) system. Unlike the conventional current- or voltage-mode square wave signaling transceivers that use binary or multilevel baseband signals, the proposed RF-I transceiver uses high-frequency modulated RF passband signals with binary phase-shift keying (BPSK) modulation. The proposed low-overhead RF-I transceiver using 0.18-µm CMOS technology achieves an aggregate data rate of 4 Gb/s/pin between four I/Os (2Tx-to-2Rx) on a shared FR4 PCB line using two carriers of 6 GHz and 12 GHz. The two transceivers occupy an area of 0.077 mm2 and dissipate a power of about 25 mW with a power efficiency of 6.25 pJ/bit.},
keywords={},
doi={10.1587/transele.E94.C.854},
ISSN={1745-1353},
month={May},}
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TY - JOUR
TI - A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects
T2 - IEICE TRANSACTIONS on Electronics
SP - 854
EP - 857
AU - Jongsun KIM
AU - Gyungsu BYUN
AU - M. Frank CHANG
PY - 2011
DO - 10.1587/transele.E94.C.854
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2011
AB - One of the most difficult problems that remains to be solved in wire interconnect architectures is the achievement of lower latency and higher concurrency on a shared bus or link without increasing the power and circuit overhead. Novel improvements in short distance on- and off-chip interconnects can be provided by using a multi-band RF interconnect (RF-I) system. Unlike the conventional current- or voltage-mode square wave signaling transceivers that use binary or multilevel baseband signals, the proposed RF-I transceiver uses high-frequency modulated RF passband signals with binary phase-shift keying (BPSK) modulation. The proposed low-overhead RF-I transceiver using 0.18-µm CMOS technology achieves an aggregate data rate of 4 Gb/s/pin between four I/Os (2Tx-to-2Rx) on a shared FR4 PCB line using two carriers of 6 GHz and 12 GHz. The two transceivers occupy an area of 0.077 mm2 and dissipate a power of about 25 mW with a power efficiency of 6.25 pJ/bit.
ER -