TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC

Hung Viet NGUYEN; Myunghwan RYU; Youngmin KIM

doi:10.1587/transele.E95.C.1864

TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC

Hung Viet NGUYEN, Myunghwan RYU, Youngmin KIM

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This paper evaluates the impact of Through-Silicon Via (TSV) on the performance and power consumption of 3D circuitry. The physical and electrical model of TSV which considers the coupling effects with adjacent TSVs is exploited in our investigation. Simulation results show that the overall performance of 3D IC infused with TSV can be improved noticeably. The frequency of the ring oscillator in 4-tier stacking layout soars up to two times compared with one in 2D planar. Furthermore, TSV process variations are examined by Monte Carlo simulations to figure out the geometrical factor having more impact in manufacturing. An in-depth research on repeater associated with TSV offers a metric to compute the optimization of 3D systems integration in terms of performance and energy dissipation. By such optimization metric with 45 nm MOSFET used in our circuit layout, it is found that the optimal number of tiers in both performance and power consumption approaches 4 since the substantial TSV-TSV coupling effect in the worst case of interference is expected in 3D IC.

Publication: IEICE TRANSACTIONS on Electronics Vol.E95-C No.12 pp.1864-1871

Publication Date: 2012/12/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E95.C.1864

Type of Manuscript: PAPER

Category: Integrated Electronics

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Hung Viet NGUYEN, Myunghwan RYU, Youngmin KIM, "TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC" in IEICE TRANSACTIONS on Electronics, vol. E95-C, no. 12, pp. 1864-1871, December 2012, doi: 10.1587/transele.E95.C.1864.
Abstract: This paper evaluates the impact of Through-Silicon Via (TSV) on the performance and power consumption of 3D circuitry. The physical and electrical model of TSV which considers the coupling effects with adjacent TSVs is exploited in our investigation. Simulation results show that the overall performance of 3D IC infused with TSV can be improved noticeably. The frequency of the ring oscillator in 4-tier stacking layout soars up to two times compared with one in 2D planar. Furthermore, TSV process variations are examined by Monte Carlo simulations to figure out the geometrical factor having more impact in manufacturing. An in-depth research on repeater associated with TSV offers a metric to compute the optimization of 3D systems integration in terms of performance and energy dissipation. By such optimization metric with 45 nm MOSFET used in our circuit layout, it is found that the optimal number of tiers in both performance and power consumption approaches 4 since the substantial TSV-TSV coupling effect in the worst case of interference is expected in 3D IC.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1864/_p

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@ARTICLE{e95-c_12_1864,
author={Hung Viet NGUYEN, Myunghwan RYU, Youngmin KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC},
year={2012},
volume={E95-C},
number={12},
pages={1864-1871},
abstract={This paper evaluates the impact of Through-Silicon Via (TSV) on the performance and power consumption of 3D circuitry. The physical and electrical model of TSV which considers the coupling effects with adjacent TSVs is exploited in our investigation. Simulation results show that the overall performance of 3D IC infused with TSV can be improved noticeably. The frequency of the ring oscillator in 4-tier stacking layout soars up to two times compared with one in 2D planar. Furthermore, TSV process variations are examined by Monte Carlo simulations to figure out the geometrical factor having more impact in manufacturing. An in-depth research on repeater associated with TSV offers a metric to compute the optimization of 3D systems integration in terms of performance and energy dissipation. By such optimization metric with 45 nm MOSFET used in our circuit layout, it is found that the optimal number of tiers in both performance and power consumption approaches 4 since the substantial TSV-TSV coupling effect in the worst case of interference is expected in 3D IC.},
keywords={},
doi={10.1587/transele.E95.C.1864},
ISSN={1745-1353},
month={December},}

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TY - JOUR
TI - TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC
T2 - IEICE TRANSACTIONS on Electronics
SP - 1864
EP - 1871
AU - Hung Viet NGUYEN
AU - Myunghwan RYU
AU - Youngmin KIM
PY - 2012
DO - 10.1587/transele.E95.C.1864
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2012
AB - This paper evaluates the impact of Through-Silicon Via (TSV) on the performance and power consumption of 3D circuitry. The physical and electrical model of TSV which considers the coupling effects with adjacent TSVs is exploited in our investigation. Simulation results show that the overall performance of 3D IC infused with TSV can be improved noticeably. The frequency of the ring oscillator in 4-tier stacking layout soars up to two times compared with one in 2D planar. Furthermore, TSV process variations are examined by Monte Carlo simulations to figure out the geometrical factor having more impact in manufacturing. An in-depth research on repeater associated with TSV offers a metric to compute the optimization of 3D systems integration in terms of performance and energy dissipation. By such optimization metric with 45 nm MOSFET used in our circuit layout, it is found that the optimal number of tiers in both performance and power consumption approaches 4 since the substantial TSV-TSV coupling effect in the worst case of interference is expected in 3D IC.
ER -