An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology

Shoichiro KAWASHIMA; Keizo MORITA; Mitsuharu NAKAZAWA; Kazuaki YAMANE; Mitsuhiro OGAI; Kuninori KAWABATA; Kazuaki TAKAI; Yasuhiro FUJII; Ryoji YASUDA; Wensheng WANG; Yukinobu HIKOSAKA; Ken'ichi INOUE

doi:10.1587/transele.E98.C.1047

An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology

Shoichiro KAWASHIMA, Keizo MORITA, Mitsuharu NAKAZAWA, Kazuaki YAMANE, Mitsuhiro OGAI, Kuninori KAWABATA, Kazuaki TAKAI, Yasuhiro FUJII, Ryoji YASUDA, Wensheng WANG, Yukinobu HIKOSAKA, Ken'ichi INOUE

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An 8-Mbit 0.18-µm CMOS 1T1C ferroelectric RAM (FeRAM) in a planar ferroelectric technology was developed. Even though the cell area of 2.48 µm² is almost equal to that of a 4-Mbit stacked-capacitor FeRAM (STACK FeRAM) 2.32 µm²[1], the chip size of the developed 8-Mbit FeRAM, including extra 2-Mbit parities for the error correction code (ECC), is just 52.37 mm², which is about 30% smaller than twice of the 4-Mbit STACK FeRAM device, 37.68mm²×2[1]. This excellent characteristic can be attributed to the large cell matrix architectures of the sectional cyclic word line (WL) that was used to increase the column numbers, and to the 1T1C bit-line GND level sensing (BGS)[2][3] circuit design intended to sense bit lines (BL) that have bit cells 1K long and a large capacitance. An access time of 52 ns and a cycle time of 77 ns in RT at a VDD of 1.8 V were achieved.

Publication: IEICE TRANSACTIONS on Electronics Vol.E98-C No.11 pp.1047-1057

Publication Date: 2015/11/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E98.C.1047

Type of Manuscript: PAPER

Category: Integrated Electronics

Authors

Shoichiro KAWASHIMA
  Fujitsu Semiconductor Limited
Keizo MORITA
  Fujitsu Semiconductor Limited
Mitsuharu NAKAZAWA
  Fujitsu Semiconductor Limited
Kazuaki YAMANE
  Fujitsu Semiconductor Limited
Mitsuhiro OGAI
  Fujitsu Semiconductor Limited
Kuninori KAWABATA
  Fujitsu Semiconductor Limited
Kazuaki TAKAI
  Fujitsu Semiconductor Limited
Yasuhiro FUJII
  Fujitsu Semiconductor Limited
Ryoji YASUDA
  Fujitsu Semiconductor Limited
Wensheng WANG
  Fujitsu Semiconductor Limited
Yukinobu HIKOSAKA
  Fujitsu Semiconductor Limited
Ken'ichi INOUE
  Fujitsu Semiconductor Limited

Keyword

1T1C-FeRAM, sectional cyclic word line, bit-line GND level sensing, planar FeRAM cell, temperature-bit distribution

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Shoichiro KAWASHIMA, Keizo MORITA, Mitsuharu NAKAZAWA, Kazuaki YAMANE, Mitsuhiro OGAI, Kuninori KAWABATA, Kazuaki TAKAI, Yasuhiro FUJII, Ryoji YASUDA, Wensheng WANG, Yukinobu HIKOSAKA, Ken'ichi INOUE, "An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology" in IEICE TRANSACTIONS on Electronics, vol. E98-C, no. 11, pp. 1047-1057, November 2015, doi: 10.1587/transele.E98.C.1047.
Abstract: An 8-Mbit 0.18-µm CMOS 1T1C ferroelectric RAM (FeRAM) in a planar ferroelectric technology was developed. Even though the cell area of 2.48 µm² is almost equal to that of a 4-Mbit stacked-capacitor FeRAM (STACK FeRAM) 2.32 µm²[1], the chip size of the developed 8-Mbit FeRAM, including extra 2-Mbit parities for the error correction code (ECC), is just 52.37 mm², which is about 30% smaller than twice of the 4-Mbit STACK FeRAM device, 37.68mm²×2[1]. This excellent characteristic can be attributed to the large cell matrix architectures of the sectional cyclic word line (WL) that was used to increase the column numbers, and to the 1T1C bit-line GND level sensing (BGS)[2][3] circuit design intended to sense bit lines (BL) that have bit cells 1K long and a large capacitance. An access time of 52 ns and a cycle time of 77 ns in RT at a VDD of 1.8 V were achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.1047/_p

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@ARTICLE{e98-c_11_1047,
author={Shoichiro KAWASHIMA, Keizo MORITA, Mitsuharu NAKAZAWA, Kazuaki YAMANE, Mitsuhiro OGAI, Kuninori KAWABATA, Kazuaki TAKAI, Yasuhiro FUJII, Ryoji YASUDA, Wensheng WANG, Yukinobu HIKOSAKA, Ken'ichi INOUE, },
journal={IEICE TRANSACTIONS on Electronics},
title={An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology},
year={2015},
volume={E98-C},
number={11},
pages={1047-1057},
abstract={An 8-Mbit 0.18-µm CMOS 1T1C ferroelectric RAM (FeRAM) in a planar ferroelectric technology was developed. Even though the cell area of 2.48 µm² is almost equal to that of a 4-Mbit stacked-capacitor FeRAM (STACK FeRAM) 2.32 µm²[1], the chip size of the developed 8-Mbit FeRAM, including extra 2-Mbit parities for the error correction code (ECC), is just 52.37 mm², which is about 30% smaller than twice of the 4-Mbit STACK FeRAM device, 37.68mm²×2[1]. This excellent characteristic can be attributed to the large cell matrix architectures of the sectional cyclic word line (WL) that was used to increase the column numbers, and to the 1T1C bit-line GND level sensing (BGS)[2][3] circuit design intended to sense bit lines (BL) that have bit cells 1K long and a large capacitance. An access time of 52 ns and a cycle time of 77 ns in RT at a VDD of 1.8 V were achieved.},
keywords={},
doi={10.1587/transele.E98.C.1047},
ISSN={1745-1353},
month={November},}

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TY - JOUR
TI - An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1047
EP - 1057
AU - Shoichiro KAWASHIMA
AU - Keizo MORITA
AU - Mitsuharu NAKAZAWA
AU - Kazuaki YAMANE
AU - Mitsuhiro OGAI
AU - Kuninori KAWABATA
AU - Kazuaki TAKAI
AU - Yasuhiro FUJII
AU - Ryoji YASUDA
AU - Wensheng WANG
AU - Yukinobu HIKOSAKA
AU - Ken'ichi INOUE
PY - 2015
DO - 10.1587/transele.E98.C.1047
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2015
AB - An 8-Mbit 0.18-µm CMOS 1T1C ferroelectric RAM (FeRAM) in a planar ferroelectric technology was developed. Even though the cell area of 2.48 µm² is almost equal to that of a 4-Mbit stacked-capacitor FeRAM (STACK FeRAM) 2.32 µm²[1], the chip size of the developed 8-Mbit FeRAM, including extra 2-Mbit parities for the error correction code (ECC), is just 52.37 mm², which is about 30% smaller than twice of the 4-Mbit STACK FeRAM device, 37.68mm²×2[1]. This excellent characteristic can be attributed to the large cell matrix architectures of the sectional cyclic word line (WL) that was used to increase the column numbers, and to the 1T1C bit-line GND level sensing (BGS)[2][3] circuit design intended to sense bit lines (BL) that have bit cells 1K long and a large capacitance. An access time of 52 ns and a cycle time of 77 ns in RT at a VDD of 1.8 V were achieved.
ER -