IEICE TRANSACTIONS on Electronics
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs
Summary :
Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E98-C No.7 pp.741-750
- Publication Date
- 2015/07/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E98.C.741
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Takashi IMAGAWA
Kyoto University
Masayuki HIROMOTO
Kyoto University
Hiroyuki OCHI
Ritsumeikan University
Takashi SATO
Kyoto University
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Takashi IMAGAWA, Masayuki HIROMOTO, Hiroyuki OCHI, Takashi SATO, "An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs" in IEICE TRANSACTIONS on Electronics,
vol. E98-C, no. 7, pp. 741-750, July 2015, doi: 10.1587/transele.E98.C.741.
Abstract: Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.741/_p
Copy
@ARTICLE{e98-c_7_741,
author={Takashi IMAGAWA, Masayuki HIROMOTO, Hiroyuki OCHI, Takashi SATO, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs},
year={2015},
volume={E98-C},
number={7},
pages={741-750},
abstract={Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.},
keywords={},
doi={10.1587/transele.E98.C.741},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs
T2 - IEICE TRANSACTIONS on Electronics
SP - 741
EP - 750
AU - Takashi IMAGAWA
AU - Masayuki HIROMOTO
AU - Hiroyuki OCHI
AU - Takashi SATO
PY - 2015
DO - 10.1587/transele.E98.C.741
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2015
AB - Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.
ER -
English
