Delay Defect Diagnosis Methodology Using Path Delay Measurements

Eun Jung JANG; Jaeyong CHUNG; Jacob A. ABRAHAM

doi:10.1587/transele.E98.C.991

Delay Defect Diagnosis Methodology Using Path Delay Measurements

Eun Jung JANG, Jaeyong CHUNG, Jacob A. ABRAHAM

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Summary :

With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design, using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.

Publication: IEICE TRANSACTIONS on Electronics Vol.E98-C No.10 pp.991-994

Publication Date: 2015/10/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E98.C.991

Type of Manuscript: BRIEF PAPER

Category: Semiconductor Materials and Devices

Authors

Eun Jung JANG
  The University of Texas
Jaeyong CHUNG
  Incheon National University
Jacob A. ABRAHAM
  The University of Texas

Keyword

VLSI testing, delay faults, delay defects, defect diagnosis, fault localization

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Eun Jung JANG, Jaeyong CHUNG, Jacob A. ABRAHAM, "Delay Defect Diagnosis Methodology Using Path Delay Measurements" in IEICE TRANSACTIONS on Electronics, vol. E98-C, no. 10, pp. 991-994, October 2015, doi: 10.1587/transele.E98.C.991.
Abstract: With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design, using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E98.C.991/_p

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@ARTICLE{e98-c_10_991,
author={Eun Jung JANG, Jaeyong CHUNG, Jacob A. ABRAHAM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Delay Defect Diagnosis Methodology Using Path Delay Measurements},
year={2015},
volume={E98-C},
number={10},
pages={991-994},
abstract={With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design, using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.},
keywords={},
doi={10.1587/transele.E98.C.991},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - Delay Defect Diagnosis Methodology Using Path Delay Measurements
T2 - IEICE TRANSACTIONS on Electronics
SP - 991
EP - 994
AU - Eun Jung JANG
AU - Jaeyong CHUNG
AU - Jacob A. ABRAHAM
PY - 2015
DO - 10.1587/transele.E98.C.991
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E98-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2015
AB - With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design, using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.
ER -