IEICE TRANSACTIONS on Fundamentals
A Design Algorithm for Sequential Circuits Using LUT Rings
Summary :
This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3342-3350
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3342
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis
Authors
Keyword
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Hiroki NAKAHARA, Tsutomu SASAO, Munehiro MATSUURA, "A Design Algorithm for Sequential Circuits Using LUT Rings" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3342-3350, December 2005, doi: 10.1093/ietfec/e88-a.12.3342.
Abstract: This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3342/_p
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@ARTICLE{e88-a_12_3342,
author={Hiroki NAKAHARA, Tsutomu SASAO, Munehiro MATSUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Design Algorithm for Sequential Circuits Using LUT Rings},
year={2005},
volume={E88-A},
number={12},
pages={3342-3350},
abstract={This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3342},
ISSN={},
month={December},}
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TY - JOUR
TI - A Design Algorithm for Sequential Circuits Using LUT Rings
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3342
EP - 3350
AU - Hiroki NAKAHARA
AU - Tsutomu SASAO
AU - Munehiro MATSUURA
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3342
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.
ER -
English
